Am29LV008T/Am29LV008B

13

PRELIMINARY

Table 5.

Am29LV008 Command Definitions

Legend:

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WEor CE pulse.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse.

SA = Address of the sector to be erased or verified. Address bits A19–A13 uniquely select any sector.

Notes:

1. All values are in hexadecimal.

2. See Table 1 for description of bus operations.

3. The data is 00h for an unprotected sector and 01h for a protected sector. The complete bus address is composed of the sector

address on A19–A13 and 02h on A7–A0.

4. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode. The Erase Suspend command

is valid only during a sector erase operation.

5. The Erase Resume command is valid only during the Erase Suspend mode.

6. Unless otherwise noted, address bits A19–A11 = X = don’t care.

Byte Programming

The device is programmed on a byte-by-byte basis.

Programming is a four-bus-cycle operation. There

are two “unlock” write cycles. These are followed by

the program command and address/data write cy-

cles. Addresses are latched on the falling edge of

CE or WE, whichever occurs later, while the data is

latched on the rising edge of CE or WE, whichever

occurs first. The rising edge of CE or WE, whichever

occurs first, initiates programming using the Em-

bedded Program Algorithm. Upon executing the

write command, the system is not required to pro-

vide further controls or timing. The device will auto-

matically provide adequate internally generated

program pulses and verify the programmed cell

margin.

The status of the Embedded Program Algorithm op-

eration can be determined three ways:

s DATA Polling of DQ7

Command

Sequence

Read/Reset

(Note 2)

Bus

Write

Cycles

Req’d

First Bus

Write Cycle

Second Bus

Read/Write

Cycle

Third Bus

Write Cycle

Fourth Bus

Read/Write

Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Reset/Read

1

XXX

F0

RA

RD

Autoselect

Manufacturer ID

3

555

AA

2AA

55

555

90

X00

01

Autoselect

Device ID

(Top Boot Block)

3

555

AA

2AA

55

555

90

X01

3E

Autoselect

Device ID

(Bottom Boot Block)

3

555

AA

2AA

55

555

90

X01

37

Autoselect

Sector Protect Verify

(Note 3)

3

555

AA

2AA

55

555

90

SA

X02

00

01

Byte Program

4

555

AA

2AA

55

555

A0

PA

PD

Chip Erase

6

555

AA

2AA

55

555

80

555

AA

2AA

55

555

10

Sector Erase

6

555

AA

2AA

55

555

80

555

AA

2AA

55

SA

30

Erase Suspend

(Note 4)

1

XXX

B0

Erase Resume

(Note 5)

1

XXX

30