TMPR4937 datasheet(219/552 Pages) TOSHIBA

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Chapter 9 SDRAM Controller

9-3

9.3

Detailed Explanation

9.3.1

Supported SDRAM configurations

This controller supports the SDRAM configurations listed below in Table 9.3.1.

The MW field of the SDRAM Channel Control Register (SDCCRn) can be used to separately set the

data bus width for each channel to either 64 bits or 32 bits.

DATA[31:0] and DQM[3:0] are used when using a 32-bit data bus. DQM[7:4] output High.

DATA[63:32] output an undefined value when DATA[31:0] become the output, but enter the High-Z

state when DATA[31:0] are the input. When in the Big Endian Mode, first external access of the upper

word (bits 63:32) of the internal data bus is performed, then external access of the lower word (bits

31:0) is performed. When in the Little Endian Mode, first external access of the lower word (bits 31:0)

is performed, then external access of the upper word (bits 63:32) is performed. When using a 32-bit data

bus, two external access will always be performed even when accessing less than 32 bits of data.

The maximum memory capacity per channel when a 64-bit data bus is configured is 1 GBytes when

using 16 512-Mbit SDRAMs with a 4-bit data bus. The total maximum memory capacity is 4 GBytes

when totaling up the four channels.

Table 9.3.1 Supported SDRAM Configurations

SDRAM Configuration

Row Address (bit)

Column Address (bit)

Remarks

1 M

× 16

2 M

× 8

16 Mbit

2-bank

4 M

× 4

See Note 1

2 M

× 32

2 M

× 32

4 M

× 16

4 M

× 16

8 M

× 8

2-bank

16 M

× 4

See Note 1

2 M

× 32

4 M

× 16

8 M

× 8

64 Mbit

4-bank

16 M

× 4

See Note 1

4 M

× 32

8 M

× 16

16 M

× 8

128 Mbit

4-bank

32 M

× 4

See Note 1

16 M

× 16

32 M

× 8

256 Mbit

4-bank

64 M

× 4

See Note 1,2

32 M

× 16

64 M

× 8

See Note 2

512 Mbit

4-bank

128 M

× 4

See Note 1,2

Note1: The SDRAM Controller logic-wise does support these configurations, but please design carefully since the memory

bus load will be large.

Note2: This SDRAM configuration has 512 Mbytes of memory on a channel. If it is mapped to physical address space

beginning with address 0, it overlaps the address space for the ROM wherein the bootstrap vectors reside.

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