TMPR4937 datasheet(225/552 Pages) TOSHIBA

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Chapter 9 SDRAM Controller

9-9

9.3.3

Initialization of SDRAM

The TX4937 Command Register has functions for generating the cycles required for initializing

SDRAM. Using software to set each register makes it possible to execute initial settings at a particular

timing.

Set the SDRAM Channel Control Register (SDCCRn).

Set the SDRAM Timing Register (SDCTR). This timing setting is applied to all channels, so please

set it to the slowest memory device.

Use the SDRAM Command Register (SDCCMD) to issue the Pre-charge All command.

Issue the Set Mode Register command in the same manner.

Set the refresh count required to initialize SDRAM to the refresh counter (SDCTR.RC)1 and set the

refresh cycle (SDCTR.RP).2 3

Wait until the refresh counter returns to “0.”

Set the refresh cycle (SDCTR.RP) to the proper value.

1 The number of refresh operations can be counted using the refresh counter. With this function, it is no longer

necessary to assemble special timing groups in the software when counting refresh operations.

2 Setting the refresh cycle to a small value makes it possible to expedite completion of the refresh cycle required for

SDRAM initialization. As described above, please set normal values after the required number of refresh cycles have

been generated.

3 Refresh requests have priority over all other SDRAM Controller access requests. Please do not set the memory

refresh cycle to an unnecessarily short value.

TMPR4937 Datasheet(PDF) 225 Page - Toshiba Semiconductor