TMPR4937 datasheet(286/552 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-28

Bit

Mnemonic

Field Name

Description

Read/Write

MDPE

Master Data

Parity Error

Master Data Parity Error (Default: 0)

Indicates the a parity error occurred when the PCI Controller is the PCI

initiator. This bit is not set when the PCI Controller is the target.

This bit is set when all of the three following conditions are met.

• It has been detected that the PERR* signal was set either directly or

indirectly.

• The PCI Controller is the Bus Master for a PCI Bus transaction during

which an error occurred.

• The Parity Error Response bit of the PCI Status Command Register

(PCISTATUS.PEREN) has been set.

R/W1C

FBBCP

Fast Back-to-

Back Capable

Fast Back-to-Back Capable (Fixed Value: 1)

Indicates whether target access of a fast back-to-back transaction can be

accepted. Is fixed to “1”.

Reserved

⎯

66MCP

66 MHz Capable

66 MHz Capable (Fixed Value: 1)

Indicates the 66 MHz operation is possible. Is fixed to “1”.

Capabilities List

Capabilities List (Fixed Value: 1)

Indicates that the capabilities list is being implemented. Is fixed to “1”.

19:10

Reserved

⎯

FBBEN

Fast Back-to-

Back Enable

Fast Back-to-Back Enable (Default: 0)

Indicates that issuing of fast back-to-back transactions has been enabled.

1: Enable

0: Disable

R/W

SEREN

SERR* Enable

SERR* Enable (Default: 0)

Enables/Disables the SERR* signal.

The SERR* signal reports that either a PCI Bus address parity error or a

special cycle data parity error was detected. The SERR* signal is only

asserted when the Parity Error Response bit is set and this bit is set.

1: Enable

0: Disable

R/W

STPC

Stepping Control

Stepping Control (Fixed Value: 0)

Indicates that stepping control is not being supported.

PEREN

Parity Error

Response

Parity Error Response (Default 0)

Sets operation when a PCI address/data parity error is detected.

A parity error response (either when the Parity Error Response bit

(PCISTATUS.PEREN) of the PERR* Signal Assert or PCI Status,

Command Register is set, or the SERR* signal is asserted) is performed

only when this bit is set.

When this bit is cleared, the PCI Controller ignores all parity errors and

continues the transaction process as if the parity of that transaction was

correct.

1: Parity error response is performed.

0: Parity error response is not performed.

R/W

VPS

VGA Palette

Snoop

VGA Palette Snoop (Fixed Value: 0)

Indicates that the VGA palette snoop function is not supported.

MWIEN

Memory Write

and Invalidate

Enable

Memory Write and Invalidate Enable (Default: 0)

Controls whether to use the Memory Write and Invalidate command instead

of the Memory Write command when the PCI Controller is the initiator.

R/W

Special Cycles

Special Cycles (Fixed Value: 0)

Indicates that special cycles will not be accepted as PCI targets.

Bus Master

Bus Master (Default: 0/1)

The default is only “1” when in the PCI Boot mode and in the Host mode.

1: Operates as the Bus Master.

0: Does not operate as the Bus Master.

R/W

Figure 10.4.2 PCI Status, Command Register (2/3)

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