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TMPR4937 Datasheet(PDF) 289 Page - Toshiba Semiconductor

Part # TMPR4937
Description  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 289 Page - Toshiba Semiconductor

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Chapter 10 PCI Controller
10-31
10.4.4 PCI Configuration 1 Register (PCICFG1) 0xD00C
The following fields correspond to the following registers.
BIST field
→ BIST Register of the PCI Configuration Space
Header Type field
→ Header Type Register in the PCI Configuration Space
Latency Timer field
→ Latency Timer Register of the PCI Configuration Space
Cache Line Size field
→ Cache Line Size Register of the PCI Configuration Space.
This register cannot be accessed when the PCI Controller is in the Satellite mode.
31
30
24
23
22
16
BISTC
Reserved
MFUNS
HT
R
R
R/L
: Type
0
0
0x00
: Initial value
15
8
7
0
LT
CLS
R/W
R/W
: Type
0x00
0x00
: Initial value
Bit
Mnemonic
Field Name
Description
Read/Write
31
BISTC
BIST Capable
BIST Capable (Fixed Value: 0)
Indicates that the BIST function is not being supported.
R
30:24
Reserved
⎯
23
MFUNS
Multi-Function
Multi-Function (Fixed Value: 0)
0: Indicates that the device is a single-function device.
R
22:16
HT
Header Type
Header Type (Default: 0x00)
Indicates the Header type.
0000000: Header Type 0
It is possible to change the header type by loading data from Configuration
EEPROM during initialization.
R/L
15:8
LT
Latency Timer
Latency Timer (Default: 0x00)
Sets the latency timer value. Specifies the PCI Bus clock count during
which to abort access when the GNT* signal is deasserted during PCI
access. Since the lower two bits are fixed to “0”, cycle counts can only be
specified in multiples of 4.
R/W
7:0
CLS
Cache Line Size
Cache Line Size (Default: 0x00)
Is used to select the PCI Bus command during a Burst Read transaction.
See “10.3.3 Supported PCI Bus Commands)” for more information.
R/W
Figure 10.4.4 PCI Configuration 1 Register



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