UPSD3422 datasheet(117/293 Pages) STMICROELECTRONICS

117 / 293 page

uPSD34xx

I2C interface

117/293

A few things to know related to these transfers:

●

Either the Master or Slave device can hold the SCL clock line low to indicate it needs

more time to handle a byte transfer. An indefinite holding period is possible.

●

A START condition is generated by a Master and recognized by a Slave when SDA has

a 1-to-0 transition while SCL is high (Figure 42 on page 117).

●

A STOP condition is generated by a Master and recognized by a Slave when SDA has

a 0-to1 transition while SCL is high (Figure 42 on page 117).

●

A RE-START (repeated START) condition generated by a Master can have the same

function as a STOP condition when starting another data transfer immediately following

the previous data transfer (Figure 42 on page 117).

●

When transferring data, the logic level on the SDA line must remain stable while SCL is

high, and SDA can change only while SCL is low. However, when not transferring data,

SDA may change state while SCL is high, which creates the START and STOP bus

conditions.

●

An Acknowlegde bit is generated from a Master or a Slave by driving SDA low during

the “ninth” bit time, just following each 8-bit byte that is transfered on the bus (Figure 42

on page 117). A Non-Acknowledge occurs when SDA is asserted high during the ninth

bit time. All byte transfers on the I2C bus include a 9th bit time reserved for an

Acknowlege (ACK) or Non-Acknowledge (NACK).

●

An additional Master device that desires to control the bus should wait until the bus is

not busy before generating a START condition so that a possible Slave operation is not

interrupted.

●

If two Master devices both try to generate a START condition simultaneously, the

Master who looses arbitration will switch immediately to Slave mode so it can

recoginize its own Slave address should it appear on the bus.

Figure 42.

Data Transfer on an I2C Bus

23.3

Operating modes

The I2C interface supports four operating modes:

●

Master-Transmitter

●

Master-Receiver

●

Slave-Transmitter

●

Slave-Receiver

MSB

7-bit Slave

Address

READ/WRITE

Indicator

Acknowledge

bits from

receiver

Start

Condition

Clock can be held low

to stall transfer.

Repeated if more

data bytes are

transferred.

Repeated

Start

Condition

Stop

Condition

3-6

3-8

MSB

ACK

NACK

R/W

AI09625

UPSD3422 Datasheet(PDF) 117 Page - STMicroelectronics

UPSD3422 Datasheet(HTML) 117 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL