UPSD3422 datasheet(114/293 Pages) STMICROELECTRONICS

114 / 293 page

IrDA interface

uPSD34xx

114/293

To produce this fixed data pulse width when the PULSE bit = 0, a prescaler is needed to

generate an internal reference clock, SIRClk, shown in Figure 39 on page 111. SIRClk is

derived by dividing the oscillator clock frequency, fOSC, using the five bits CDIV[4:0] in the

SFR named IRDACON. A divisor must be chosen to produce a frequency for SIRClk that

lies between 1.34 MHz and 2.13 MHz, but it is best to choose a divisor value that produces

SIRClk frequency as close to 1.83MHz as possible, because SIRClk at 1.83MHz will

produce an fixed IrDA data pulse width of 1.63µs. Table 53 provides recommended values

for CDIV[4:0] based on several different values of fOSC.

For reference, SIRClk of 2.13MHz will generate a fixed IrDA data pulse width of 1.41µs, and

SIRClk of 1.34MHz will generate a fixed data pulse width of 2.23µs.

Table 53.

Recommended CDIV[4:0] values to generate SIRClk (default CDIV[4:0] =

0Fh, 15 decimal)

Note:

When PULSE bit = 0 (fixed data pulse width), this is minimum recommended fOSC because

CDIV[4:0] must be 4 or greater.

fOSC (MHz)

Value in CDIV[4:0]

Resulting fSIRCLK (MHz)

40.00

16h, 22 decimal

1.82

36.864, or 36.00

14h, 20 decimal

1.84, or 1.80

24.00

0Dh, 13 decimal

1.84

11.059, or 12.00

06h, 6 decimal

1.84, or 2.00

7.3728(1)

04h, 4 decimal

1.84

UPSD3422 Datasheet(PDF) 114 Page - STMicroelectronics