UPSD3422 datasheet(199/293 Pages) STMICROELECTRONICS

199 / 293 page

uPSD34xx

PSD module

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The Flash memories are 16-bit wide when it is in Program Memory space and are 8-bit wide

when it is in the Data Space. When the Flash memory is configured in both “Program

Space” and “Data Space,” the Flash will drive 16-bit in a PSEN cycle and operates as an 8-

bit memory in READ or WRITE cycle.

The SRAM, csiop, and external device are always in 8-bit data space.

Table 105.

Data width in different bus cycles

Note:

x = NA

28.4

Runtime control register definitions (csiop)

The 39 csiop registers are defined in Table 106. The 8032 can access each register by the

address offset (specified in Table 106) added to the csiop base address that was specified

in PSDsoft Express. Do not write to unused locations within the csiop block of 256 registers,

they should remain logic zero.

Table 106.

CSIOP registers and their offsets (in hexadecimal)

Type of Bus Cycle

Main Flash

Secondary

Flash

SRAM

CSIOP

External

Device

PSEN Cycle (Program Memory)

16-bit

Read or Write Cycle (Data Memory)

8-bit

Flash Programming Cycle (Flash Write

or Reading Status)

8-bit

xxx

Name

Port A

(80-pin)

Port B Port C Port D Other

Description

Link

Data In

00h

01h

10h

11h

MCU I/O input mode. Read to

obtain current logic level of pins

on Ports A, B, C, or D. No

WRITEs.

Table 122

page 228

Control

02h

03h

Selects MCUI/O or Latched

Address Out mode. Logic 0 =

MCU I/O, 1 = 8032 Addr Out.

Write to select mode. Read for

status.

Table 134

page 232

Data Out

04h

05h

12h

13h

MCU I/O output mode. Write to

set logic level on pins of Ports

A, B, C, or D. Read to check

status. This register has no

effect if a port pin is driven by

an OMC output from PLD.

Table 126

page 229

Direction

06h

07h

14h

15h

MCU I/O mode. Configures

port pin as input or output.

Write to set direction of port

pins.

Logic 1 = out, Logic 0 = in.

Read to check status.

Table 130

page 229

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