UPSD3422 datasheet(281/293 Pages) STMICROELECTRONICS

281 / 293 page

uPSD34xx

DC and AC parameters

281/293

Note:

For non-PLD Programming, Erase or in ISC By-pass Mode.

For Program or Erase PLD only.

Table 181.

ISC timing (3V PSD module)

Note:

For non-PLD Programming, Erase or in ISC By-pass Mode.

For Program or Erase PLD only.

Figure 109. MCU module AC measurement I/O waveform

Note:

AC inputs during testing are driven at VCC–0.5V for a logic '1,' and 0.45V for a logic '0.'

Note:

Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0'

tISCPCO ISC Port Clock to Output

tISCPZV ISC Port High-Impedance to Valid Output

tISCPVZ ISC Port Valid Output to High-Impedance

Symbol

Parameter

Conditions

Min

Max

Unit

Symbol

Parameter

Conditions

Min

Max

Unit

tISCCF

Clock (TCK, PC1) Frequency (except for

PLD)

(Note 1)

MHz

tISCCH

Clock (TCK, PC1) High Time (except for

PLD)

(Note 1)

tISCCL

Clock (TCK, PC1) Low Time (except for

PLD)

(Note 1)

tISCCFP Clock (TCK, PC1) Frequency (PLD only)

(Note 2)

MHz

tISCCHP Clock (TCK, PC1) High Time (PLD only)

(Note 2)

tISCCLP Clock (TCK, PC1) Low Time (PLD only)

(Note 2)

tISCPSU ISC Port Set Up Time

tISCPH

ISC Port Hold Up Time

tISCPCO ISC Port Clock to Output

tISCPZV ISC Port High-Impedance to Valid Output

tISCPVZ ISC Port Valid Output to High-Impedance

AI06650

VCC – 0.5V

0.45V

Test Points

0.2 VCC – 0.1V

0.2 VCC + 0.9V

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