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UPSD3422 Datasheet(PDF) 280 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 280 Page - STMicroelectronics |
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280 / 293 page  DC and AC parameters uPSD34xx 280/293 Table 179. VSTBYON definitions timing (5V, 3V PSD modules) Note: 1 VSTBYON timing is measured at VCC ramp rate of 2ms. Figure 108. ISC timing Table 180. ISC timing (5V PSD module) Symbol Parameter Conditions Min Typ Max Unit tBVBH VSTBY Detection to VSTBYON Output High (Note 1) 20 µs tBXBL VSTBY Off Detection to VSTBYON Output Low (Note 1) 20 µs Symbol Parameter Conditions Min Max Unit tISCCF Clock (TCK, PC1) Frequency (except for PLD) (Note 1) 20 MHz tISCCH Clock (TCK, PC1) High Time (except for PLD) (Note 1) 23 ns tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1) 23 ns tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2) 4 MHz tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2) 90 ns tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2) 90 ns tISCPSU ISC Port Set Up Time 7 ns tISCPH ISC Port Hold Up Time 5 ns ISCCH TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO t ISCCL t ISCPH t ISCPSU t ISCPVZ t ISCPZV t ISCPCO t AI02865 |
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