UPSD3422 datasheet(277/293 Pages) STMICROELECTRONICS

277 / 293 page

uPSD34xx

DC and AC parameters

277/293

Table 172.

Input macrocell timing (3V PSD module)

Note:

Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings

refer to tAVLX and tLXAX.

Table 173.

Program, WRITE and erase times (5V, 3V PSD modules)

Note:

Programmed to all zero before erase.

Typical after 100K Write/Erase cycles is 5 seconds.

The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid

for reading.

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Unit

tIS

Input Setup Time

(Note 1)

tIH

Input Hold Time

(Note 1)

+ 15

tINH

NIB Input High Time

(Note 1)

tINL

NIB Input Low Time

(Note 1)

tINO

NIB Input to Combinatorial

Delay

(Note 1)

+ 4

+ 15

Symbol

Parameter

Min.

Typ.

Max.

Unit

Flash Program

8.5

Flash Bulk Erase(1) (pre-programmed)

3(2)

Flash Bulk Erase (not pre-programmed)

tWHQV3

Sector Erase (pre-programmed)

tWHQV2

Sector Erase (not pre-programmed)

2.2

tWHQV1

Byte Program

150

µs

Program / Erase Cycles (per Sector)

100,000

cycles

PLD Program / Erase Cycles

1,000

cycles

tWHWLO

Sector Erase Time-Out

100

µs

tQ7VQV

DQ7 Valid to Output (DQ7-DQ0) Valid (Data

Polling)(3)

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