UPSD3422 datasheet(274/293 Pages) STMICROELECTRONICS

274 / 293 page

DC and AC parameters

uPSD34xx

274/293

Table 167.

CPLD macrocell synchronous clock mode timing (5V PSD module)

Note:

Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by

given amount.

2CLKIN (PD1) tCLCL = tCH + tCL.

Table 168.

CPLD Macrocell Synchronous Clock Mode Timing (3V PSD Module)

Note:

Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by

given amount.

2CLKIN (PD1) tCLCL = tCH + tCL.

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Slew

rate(1)

Unit

fMAX

Maximum Frequency

External Feedback

1/(tS+tCO)

40.0

MHz

Maximum Frequency

Internal Feedback (fCNT)

1/(tS+tCO–

10)

66.6

MHz

Maximum Frequency

Pipelined Data

1/(tCH+tCL)

83.3

MHz

Input Setup Time

+ 2

+ 10

Input Hold Time

tCH

Clock High Time

Clock Input

tCL

Clock Low Time

Clock Input

tCO

Clock to Output Delay

Clock Input

– 2

tARD

CPLD Array Delay

Any

macrocell

+ 2

tMIN

Minimum Clock Period(2)

tCH+tCL

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Slew

rate(1)

Unit

fMAX

Maximum Frequency

External Feedback

1/(tS+tCO)

23.2

MHz

Maximum Frequency

Internal Feedback (fCNT)

1/(tS+tCO–10)

30.3

MHz

Maximum Frequency

Pipelined Data

1/(tCH+tCL)

40.0

MHz

Input Setup Time

+ 4

+ 15

Input Hold Time

tCH

Clock High Time

Clock Input

tCL

Clock Low Time

Clock Input

tCO

Clock to Output Delay

Clock Input

– 6

tARD

CPLD Array Delay

Any macrocell

+ 4

tMIN

Minimum Clock Period(2)

tCH+tCL

UPSD3422 Datasheet(PDF) 274 Page - STMicroelectronics

UPSD3422 Datasheet(HTML) 274 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL