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TMP92CD54IF Datasheet(PDF) 77 Page - Toshiba Semiconductor |
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TMP92CD54IF Datasheet(HTML) 77 Page - Toshiba Semiconductor |
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77 / 343 page  2006-01-27 92CD54I-77 TMP92CD54I 3.7.2 Operation of each circuit (1) Prescalers A 9-bit prescaler generates the input clock to timers 01. The clock T0 is the CPU clock fc divided by 4 and is the input to this prescaler. The prescaler’s operation can be controlled using TRUN01<T01PRUN> in the timer control register. Setting <T01PRUN> to 1 starts the count; setting <T10PRUN> to 0 clears the prescaler to zero and stops operation. At fc=20MHz Output clock Interval φT1 (8/fc) φT4 (32/fc) φT16 (128/fc) φT256 (2048/fc) 400 ns 1.6 µs 6.4 µs 102.4 µs 0 1 2 3 4 5 6 7 8 9-bit prescaler O S C X1 X2 ×4 ÷2 (10MHz) (10MHz) ÷4 ÷2 φT0 φT1 φT4 φT16 φT256 φT2 φT8 φT32 run/stop & clear TRUN01<T01PRUN> fIO (internal I/O clock) CPU clock fc (20MHz) . 4/fc φT1 φT4 Figure 3.7.5 Prescaler Note: The following number in the parenthesis indicates the frequency when TMP92CD54I operates is the maximum frequency. |
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