TMP92CD54IF datasheet(21/343 Pages) TOSHIBA

21 / 343 page

2006-01-27

92CD54I-21

TMP92CD54I

3.4 Interrupts

Interrupts are controlled by the CPU Interrupt Mask Register <IFF2:0> (bits 12 to 14 of the

Status Register) and by the built-in interrupt controller.

TMP92CD54I has a total of 60 interrupts divided into the following five types:

Interrupts generated by CPU: 9 sources

• Software interrupts: 8 sources

• Illegal Instruction interrupt: 1 source

Internal interrupts: 42 sources

• Internal I/O interrupts: 34 sources

• Micro DMA Transfer End interrupts: 8 sources

External interrupts: 9 sources

• Interrupts on external pins ( NMI, INT0 to INT7)

A fixed individual interrupt vector number is assigned to each interrupt source.

Any one of six levels of priority can also be assigned to each maskable interrupt. Non-maskable

interrupts have a fixed priority level of 7, the highest level.

When an interrupt is generated, the interrupt controller sends the priority of that interrupt to

the CPU. When more than one interrupt are generated simultaneously, the interrupt controller

sends the priority value of the interrupt with the highest priority to the CPU. (The highest priority

level is 7, the level used for non-maskable interrupts.)

The CPU compares the interrupt priority level which it receives with the value held in the CPU

Interrupt Mask Register <IFF2:0>. If the priority level of the interrupt is greater than or equal to

the value in the Interrupt Mask Register, the CPU accepts the interrupt.

However, software interrupts and Illegal Instruction interrupts generated by the CPU are

processed irrespective of the value in <IFF2:0>.

The value in the Interrupt Mask Register <IFF2:0> can be changed using the EI instruction (EI

num sets <IFF2:0> to num). For example, the command EI 3 enables the acceptance of all

non-maskable interrupts and of maskable interrupts whose priority level, as set in the interrupt

controller, is 3 or higher. The commands EI and EI 0 enable the acceptance of all non-maskable

interrupts and of maskable interrupts with a priority level of 1 or above (hence both are equivalent

to the command EI 1).

The DI instruction (sets <IFF2:0> to 7) is exactly equivalent to the EI 7 instruction. The DI

instruction is used to disable all maskable interrupts (since the priority level for maskable

interrupts ranges from 0 to 6). The EI instruction takes effect as soon as it is executed.

In addition to the general-purpose Interrupt Processing Mode described above, there is also a

Micro DMA Processing Mode.

In Micro DMA Mode the CPU automatically transfers data in one-byte, two-byte or four-byte

blocks; this mode allows high-speed data transfer to and from internal and external memory and

internal I/O ports.

In addition, TMP92CD54I also has a software start function in which micro DMA processing is

requested in software rather than by an interrupt.

Figure 3.4.1 is a flowchart showing overall interrupt processing.

TMP92CD54IF Datasheet(PDF) 21 Page - Toshiba Semiconductor

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