| Electronic Components Datasheet Search |
|
UPSD3422EB40U6 Datasheet(PDF) 272 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
UPSD3422EB40U6 Datasheet(HTML) 272 Page - STMicroelectronics |
|
272 / 293 page ![]() DC and AC parameters uPSD34xx 272/293 Table 164. USB transceiver specification Note: 1 Temperature range = –45°C to 85°C. 2 This value includes an external resistor of 24 Ω ±1%. Figure 101. Input to output disable / enable Table 165. CPLD combinatorial timing (5V PSD module) Symbol Parameter Test Conditions(1) Min. Typ. Max. Unit UVOH High Output Voltage VDD = 3.3V; IOUT = 2.2mA 3– V UVOL Low Output Voltage VDD = 3.3V; IOUT = 2.2mA –0.25 V UVIH High Input Voltage VDD = 3.6V 2 – V UVIL Low Input Voltage VDD = 3.6V 0.8 V RDH Output Impedance (high state) Note 2 28 43 Ω RDL Output Impedance (low state) Note 2 28 43 Ω IL Input Leakage Current VDD = 3.6V ±0.1 ±5 µA IOZ 3-state Output OFF State Current VI = VIH or VIL ±10 µA VCR Crossover Point 1.3 2 V tRISE Rise Time 4 20 ns tFALL Fall Time 4 20 ns Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate(1) Unit tPD (2) CPLD Input Pin/Feedback to CPLD Combinatorial Output 20 + 2 + 10 – 2 ns tEA CPLD Input to CPLD Output Enable 21 + 10 – 2 ns tER CPLD Input to CPLD Output Disable 21 + 10 – 2 ns tARP CPLD Register Clear or Preset Delay 21 + 10 – 2 ns tER tEA INPUT INPUT TO OUTPUT ENABLE/DISABLE AI02863 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |