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DF6808 Datasheet(PDF) 3 Page - Digital Core Design |
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DF6808 Datasheet(HTML) 3 Page - Digital Core Design |
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3 / 9 page ![]() All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. ♦ ◊ ◊ ◊ ♦ ◊ ◊ ◊ ♦ ◊ ◊ ◊ ♦ ♦ ♦ ◊ ◊ ○ http://www.DigitalCoreDesign.com http://www.dcd.pl DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF VHDL & VERILOG test bench environ- ment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance ● Delivery the IP Core updates, minor and major versions changes ● Delivery the documentation updates Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementa- tion. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bit- streams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restric- tion except One Year license where time of use is limited to 12 months. ● ○ Single Design license for VHDL, Verilog source code called HDL Sour- ce ○ Encrypted, or plain text EDIF called Netlist ● ○ ● ○ ○ ● ○ ○ One Year license for Encrypted Netlist only Unlimited Designs license for HDL Source Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs CONFIGURATION The following parameters of the DF6808 core can be easy adjusted to requirements of dedicated application and technology. Con- figuration of the core can be prepared by ef- fortless changing appropriate constants in package file. There is no need to change any parts of the code. - used • DoCD TM Hardware Debugger - unused - Harvard • Architecture type - Von Neumann - Synchronous • Memories type - Asynchronou - used • Data Memory wait-states - unused - used • Power saving STOP mode - unused - used • WATCHDOG Timer - unused - used • Timer system - unused - used • Compare Capture channels - unused - used • PORTS A, B, C, D - unused - used • SCI – UART Interface - unused - used • SPI Interface - unused - used • Support for DIV Instructions - unused - used • Support for MUL Instruction - unused - used • Support for DAA Instruction - unused |
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