All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

OPTIONAL

PERIPHERALS

There are also available an optional pe-

ripherals, not included in presented DF6808

Microcontroller Core. The optional peripherals,

can be implemented in microcontroller core

upon customer request.

I2C bus controller - Master

7-bit and 10-bit addressing modes

NORMAL, FAST, HIGH speeds

Multi-master systems supported

Clock arbitration and synchronization

User defined timings on I2C lines

Wide range of system clock frequencies

Interrupt generation

I2C bus controller - Slave

NORMAL speed 100 kbs

FAST speed 400 kbs

HIGH speed 3400 kbs

Wide range of system clock frequencies

User defined data setup time on I2C lines

Interrupt generation

PWM – Pulse Width Modulation Timer

Fixed-Point arithmetic coprocessor

Floating-Point

arithmetic

coprocessor

IEEE-754 standard single precision

PERFORMANCE

The following table gives a survey about

the Core area and performance in the

ALTERA® devices after Place & Route:

Device

Speed

grade

Logic Cells

CYCLONE

-6

2635

61 MHz

CYCLONE II

-6

2635

65 MHz

STRATIX

-5

2636

65 MHz

STRATIX II

-3

2124

96 MHz

STRATIX GX

-5

2636

66 MHz

APEX20KC

-7

2531

48 MHz

APEX20KE

-1

2531

41 MHz

ACEX1K

-1

2536

36 MHz

FLEX10KE

-1

2536

36 MHz

Core performance in ALTERA® devices

Area utilized by the each unit of DF6808 core

in vendor specific technologies is summarized

in table below.

Component

Area

[LC]

[FFs]

CPU*

1 780

214

Main Timer

110

55

COM/CAP

150

60

Watchdog

29

14

SPI Interface

131

62

UART - SCI

272

124

I/O Ports

161

64

Total area

2 635

593

*CPU – consisted of ALU, Control Unit and Instruction Decoder, Bus

Controller with support for 64KB RAM, External IRQ pin Interrupt Con-

troller

Core components area utilization