All trademarks mentioned in this document

http://www.DigitalCoreDesign.com

are trademarks of their respective owners.

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

from IDLE condition

DELIVERABLES

♦

Source code:

◊

VHDL Source Code or/and

◊

VERILOG Source Code or/and

◊

Encrypted, or plain text EDIF

♦

VHDL & VERILOG test bench environ-

ment

◊

Active-HDL automatic simulation macros

◊

ModelSim automatic simulation macros

◊

Tests with reference responses

♦

Technical documentation

◊

Installation notes

◊

HDL core specification

◊

Datasheet

♦

Synthesis scripts

♦

Example application

♦

Technical support

◊

IP Core implementation support

◊

3 months maintenance

●

Delivery the IP Core updates, minor

and major versions changes

●

Delivery the documentation updates

LICENSI N G

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Unlimited Designs, One Year

licenses allow

use IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

CONFIGURATI O N

The following parameters of the DF6811 core

can be easy adjusted to requirements of

dedicated application and technology. Con-

figuration of the core can be prepared by ef-

fortless

changing appropriate constants in

package file. There is no need to change any

parts of the code.

-

used

-

unused

-Harvard

-

Von Neumann

-

Synchronous

-

Asynchronou

-

64 kB

-

16 MB

-

used

-

unused

-

used

-

unused

-

used

-

unused

-

used

-

unused

-

used

-

unused

-

used

-

unused

-

used

-

unused

-

used

-

unused

-

used

•

Support for MUL and DIV

Instructions

-

unused