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D

1

8-bit FAST Microcontrollers Family

ver 3.01

OVERVIEW

Document contains brief description of

DF6811 core functionality. The DF6811 is a

advanced 8-bit MCU IP Core with highly so-

phisticated, on chip peripheral capabilities.

DF6811 soft core is binary-compatible with the

industry standard 68HC11 8-bit microcontrol-

ler and can achieve a performance 45-100

million instructions

per second. The DF6811

has FAST architecture that is 4 times faster

compared to original implementation. Core in

standard configuration has integrated on chip

major peripheral function. There are two serial

interfaces: an asynchronous serial communi-

cations interface (SCI) and a separate syn-

chronous serial peripheral interface (SPI). The

main 16-bit, free-running timer system has

implemented three input capture lines, five

output-compare lines, and a real-time interrupt

function. An 8-bit pulse accumulator subsys-

tem can count external events or measure

external periods.

Self-monitoring circuitry is included on-chip to

protect against system errors. A computer

operating properly (COP) watchdog system

protects against software failures. An illegal

opcode detection circuit provides a non-

maskable interrupt if illegal opcode is de-

tected. Two software-controlled power-saving

modes, WAIT and STOP, are available to

conserve additional power. These modes

make the DF6811 IP Core especially attrac-

tive for automotive and battery-driven applica-

tions. The DF6811 have built in the develop-

ment support features designed into DF6811.

The LIR signal is intended as a debugging aid.

This signal is driven to active low for the first

bus cycle of each new instruction, making it

easy to reverse assemble (disassemble) in-

structions from the display of a logic analyzer.

DF6811 is fully customizable, which means

it is delivered in the exact configuration to

meet users requirements. There is no need to

pay extra for not used features and wasted

silicon.

It includes fully automated testbench

with complete set of tests allowing easy

package validation at each stage of SoC de-

sign flow.

CPU FEATURES

original implementation

dard 68HC11

Registers space (SFRs)

easy connection to memory

slow program and data memories