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TMP88CS38FG Datasheet(PDF) 98 Page - Toshiba Semiconductor

Part # TMP88CS38FG
Description  8-bit single chip microcomputer
PDF  226 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP88CS38FG Datasheet(HTML) 98 Page - Toshiba Semiconductor

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TMP88CS38/CM38A/CP38A
2007-09-12
88CS38-98
(3) 1-word data transfer
Check the MST by the INTSBI interrupt process after an 1-word data transfer is
completed, and determine whether the mode is a master or slave.
a. When the MST is “1” (Master mode)
Check the TRX and determine whether the mode is a transmitter or receiver.
1. When the TRX is “1” (Transmitter mode)
Test the LRB. When the LRB is “1”, a receiver does not request data. Implement
the process to generate a stop condition (Described later) and terminate data
transfer.
When the LRB is “0”, the receiver requests next data. When the next
transmitted data is other than 8 bits, set the BC, set the ACK to “1”, and write the
transmitted data to the SBIDBR. After writing the data, the PIN becomes “1”, a
serial clock pulse is generated for transferring a next 1 word of data from the SCL
pin, and then the 1 word data is transmitted. After the data is transmitted, and an
INTSBI interrupt request occurs. The PIN become “0” and the SCL pin is set to
low level. If the data to be transferred is more than one word in length, repeat the
procedure from the LRB test above.
Figure 2.9.14 Example of when BC
= “000”, ACK = “1”
2. When the TRX is “0” (Receiver mode)
When the next transmitted data is other than of 8 bits, set the BC again. Set the
ACK to “1” and read the received data from the SBIDBR (Reading data is
undefined immediately after a slave address is sent). After the data is read, the
PIN becomes “1”. A serial bus interface circuit outputs a serial clock pulse to the
SCL to transfer next 1 word of data and sets the SDA pin to “0” at the
acknowledge signal timing.
An INTSBI interrupt request occurs and the PIN becomes “0”. Then a serial bus
interface circuit outputs a clock pulse for 1 word of data transfer and the
acknowledge signal each time that received data is read from the SBIDBR.
Figure 2.9.15 Example of when BC
= “000”, ACK = “1”
SCL pin
SDA pin
Acknowledge
signal from a
receiver
1
2
34
567
89
D7
D6
D5
D4
D3
D2
D1
PIN
INTSBI interrupt
request
D0
Write to SBIDBR
SCL pin
SDA pin
Acknowledge
signal to a
transmitter
1
2
345
678
9
D7
D6
D5
D4
D3
D2
D1
PIN
INTSBI interrupt
D0
Read to SBIDBR
New D7



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