TMP86FS64FG datasheet(147/252 Pages) TOSHIBA

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Page 135

TMP86FS64FG

13.3.4 Pulse Width Modulation (PWM) Output Mode

The pulse width modulation (PWM) output mode is used to generate the PWM pulse with up to 8 bits of res-

olution by an internal clock.

When a match between the up-counter and the TC6DR value is detected, the logic level output from the

PWM

6 pin becomes low. The up-counter continues counting. When the up-counter overflow occurs, the PWM6

pin becomes high. The INTTC6 interrupt request is generated at this time.

When the timer is stopped, the PWM6 pin is high. Therefore, if the timer is stopped when the PWM6 pin is

low, one PMW cycle may be shorter than the programmed value.

TC6DR is serially connected to the shift register. If TC6DR is programmed during PWM output, the data set

to TC6DR is not shifted until one PWM cycle is completed. Therefore, a pulse can be modulated periodically.

For the first time, the data written to TC6DR is shifted when the timer is started by setting TC6CR<TC6S> to

Note 1: The PWM output mode can be used only in the NORMAL1/2 and IDEL 1/2 modes.

Note 2: In the PWM output mode, program TC6DR immediately after the INTTC6 interrupt request is generated

(typically in the INTTC6 interrupt service routine.) When the programming of TC6DR and the INTTC6 inter-

rupt occur at the same time, an unstable value is shifted, that may result in generation of pulse different

from the programmed value until the next INTTC6 interrupt request is issued.

Figure 13-3 PWM output Mode Timing Chart (TC6)

Internal clock

Shift register

Counter

n + 1

PWM cycle

Match detect

Data shift

Rewrite

Data shift

Match detect

Data shift

Rewrite

PWM6 pin

INTTC6

interrupt request

Timer F/F

TC6DR

TC6CR<TC6S>

TMP86FS64FG Datasheet(PDF) 147 Page - Toshiba Semiconductor