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TMP86CS64AFG Datasheet(PDF) 61 Page - Toshiba Semiconductor |
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TMP86CS64AFG Datasheet(HTML) 61 Page - Toshiba Semiconductor |
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61 / 202 page  Page 51 TMP86CS64AFG 4. Special Function Register (SFR) The TMP86CS64AFG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH. This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for TMP86CS64AFG. 4.1 SFR Address Read Write 0000H P0DR 0001H P1DR 0002H P2DR 0003H P3DR 0004H P4DR 0005H P5DR 0006H P6DR 0007H P7DR 0008H P0CR 0009H P1CR 000AH P4PRD - 000BH P3CR 000CH P4CR 000DH P5CR 000EH ADCCR1 000FH ADCCR2 0010H TC3DRA 0011H TC3DRB - 0012H TC3CR 0013H TC2CR 0014H TC4CR 0015H TC5CR 0016H TC6CR 0017H TC6DR 0018H TC4DR 0019H TC5DR 001AH IRDACR 001BH UARTSR UARTCR1 001CH - UARTCR2 001DH RDBUF TDBUF 001EH Reserved 001FH Reserved 0020H TC1DRAL 0021H TC1DRAH 0022H TC1DRBL 0023H TC1DRBH 0024H TC2DRL 0025H TC2DRH |
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