TMP86CS64AFG datasheet(174/202 Pages) TOSHIBA

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Page 164

16. Synchronous Serial Interface (SIO2)

16.6 Transfer Mode

TMP86CS64AFG

Figure 16-8 Transfer Mode (Example: 8bit, 1word transfer, External clock)

Figure 16-9 Transmiiied Data Hold Time at End of Transfer

16.6.2 4-bit and 8-bit receive modes

After setting the control registers to the receive mode, set SIO2CR1<SIOS> to “1” to enable receiving. The

data are then transferred to the shift register via the SI pin in synchronous with the serial clock. When one word

of data has been received, it is transferred from the shift register to the data buffer register (DBR). When the

number of words specified with the SIO2CR2<BUF> has been received, an INTSIO2 (Buffer full) interrupt is

generated to request that these data be read out. The data are then read from the data buffer registers by the

interrupt service program.

When the internal clock is used, and the previous data are not read from the data buffer register before the

next data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read.

A wait will not be initiated if even one data word has been read.

Note:Waits are also canceled by reading a DBR not being used as a received data buffer register is read; therefore,

during SIO2 do not use such DBR for other applications.

DBR

Clear SIOS

Write

(a)

Write

(b)

SCK2 pin

(Input)

SO2 pin

INTSIO2 interrupt

SIO2CR1<SIOS>

SIO2SR<SIOF>

SIO2SR<SEF>

MSB of last word

tSODH = min 3.5/fc [s] ( In the NORMAL1/2, IDLE1/2 modes)

tSODH = min 3.5/fs [s] (In the SLOW1/2, SLEEP1/2 modes)

SCK2 pin

SO2 pin

SIO2SR<SIOF>

TMP86CS64AFG Datasheet(PDF) 174 Page - Toshiba Semiconductor