M58BW016DB datasheet(48/69 Pages) STMICROELECTRONICS

48 / 69 page

DC and AC parameters

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

48/69

Figure 14.

Synchronous Burst Read (data valid from ‘n’ clock rising edge)

For set up signals and timings see Synchronous Burst Read.

Table 20.

Synchronous Burst Read AC characteristics(1)

For other timings see Table 16: Asynchronous Bus Read AC characteristics.

Symbol

Parameter

Test condition

M58BW016

Unit

tAVLL

Address Valid to Latch Enable Low

E =VIL

Min

tBHKH

Burst Address Advance High to Valid

Clock Edge

E =VIL, G =VIL, L =VIH

Min

tBLKH

Burst Address Advance Low to Valid

Clock Edge

E =VIL, G =VIL, L =VIH

Min

tELLL

Chip Enable Low to Latch Enable low

Min

tGLQV Output Enable Low to Output Valid

E =VIL, L =VIH

Min

tKHAX

Valid Clock Edge to Address

Transition

E =VIL

Min

tKHLL

Valid Clock Edge to Latch Enable Low

E =VIL

Min

tKHLX

Valid Clock Edge to Latch Enable

Transition

E =VIL

Min

tKHQX Valid Clock Edge to Output Transition

E =VIL,

G =VIL,

L =VIH

M58BW016DT/B Min

M58BW016FT/B Min

tLLKH

Latch Enable Low to Valid Clock Edge E =VIL

M58BW016DT/B Min

M58BW016FT/B Min

tQVKH

(2)

Data output should be read on the valid clock edge.

Output Valid to Valid Clock Edge

E =VIL, G =VIL, L =VIH

Min

tRLKH

Valid Data Ready Low to Valid Clock

Edge

E =VIL, G =VIL, L =VIH

Min

tKHQV Valid Clock Edge to Output Valid

E =VIL, G =VIL, L =VIH Max

AI04408b

n+5

n+4

n+3

n+2

n+1

DQ0-DQ31

tQVKH

tKHQX

SETUP

Burst Read

Q0 to Q3

tKHQV

Note: n depends on Burst X-Latency

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