Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

HM1-6514S/883 Datasheet(PDF) 7 Page - Renesas Technology Corp

Part # HM1-6514S/883
Description  1024 x 4 CMOS RAM
PDF  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HM1-6514S/883 Datasheet(HTML) 7 Page - Renesas Technology Corp

  HM1-6514S/883 Datasheet HTML 1Page - Renesas Technology Corp HM1-6514S/883 Datasheet HTML 2Page - Renesas Technology Corp HM1-6514S/883 Datasheet HTML 3Page - Renesas Technology Corp HM1-6514S/883 Datasheet HTML 4Page - Renesas Technology Corp HM1-6514S/883 Datasheet HTML 5Page - Renesas Technology Corp HM1-6514S/883 Datasheet HTML 6Page - Renesas Technology Corp HM1-6514S/883 Datasheet HTML 7Page - Renesas Technology Corp HM1-6514S/883 Datasheet HTML 8Page - Renesas Technology Corp HM1-6514S/883 Datasheet HTML 9Page - Renesas Technology Corp  
Zoom Inzoom in Zoom Outzoom out
 7 / 9 page
background image
HM-6514/883
FN2996 Rev.1.00
Page 7 of 9
March 1997
Timing Waveforms (Continued)
The write cycle is initiated by the falling edge of E (T = 0),
which latches the address information in the on-chip registers.
There are two basic types of write cycles, which differ in the
control of the common data-in/data-out bus.
Case 1: E falls before W falls
The output buffers may become enabled (reading) if E falls
before W falls. W is used to disable (three-state) the outputs so
input data can be applied. TWLDV must be met to allow the W
signal time to disable the outputs before applying input data.
Also, at the end of the cycle the outputs may become active if
W rises before E. The RAM outputs and all inputs will three-
state after E rises (TEHQZ). In this type of write cycle TWLEL
and TEHWH may be ignored.
Case 2: E falls equal to or after W falls, and E rises before
or equal to W rising
This E and W control timing will guarantee that the data out-
puts will stay disabled throughout the cycle, thus simplifying
the data input timing. TWLEL and TEHWH must be met, but
TWLDV becomes meaningless and can be ignored. In this
cycle TDVWH and TWHDX become TDVEH and TEHDX. In
other words, reference data setup and hold times to the E ris-
ing edge.
If a series of consecutive write cycles are to be performed, W
may be held low until all desired locations have been written
(an extension of Case 2).
TAVEL
TELWL
TEVEL
TELAX
TWHEH
HIGH Z
HIGH Z
TWHDZ
-1
TIME
01
2
3
4
5
REFERENCE
VALID ADD
NEXT ADD
TELEL
TEHEL
TELEH
TWLEH
TWLWH
TEHEL
TWLDV
VALID DATA INPUT
TDVWH
TELWH
W
DQ
E
A
FIGURE 2. WRITE CYCLE
TRUTH TABLE
TIME
REFERENCE
INPUTS
DQ
FUNCTION
E
W
A
-1
H
X
X
Z
Memory Disabled
0
X
V
Z
Cycle Begins, Addresses are Latched
1
L
L
X
Z
Write Period Begins
2
L
X
V
Data In is Written
3H
X
Z
Write Completed
4
H
X
X
Z
Prepare for Next Cycle (Same as -1)
5
X
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
IF
OBSERVE
IGNORE
Case 1
E falls before W
TWLDV
TWLEL
Case 2
E falls after W and
E rises before W
TWLEL
TEHWH
TWLDV
TWHDX



Html Pages

1 2 3 4 5 6 7 8 9


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com