ASIX ELECTRONICS CORPORATION

10

AX88772

USB to 10/100 Fast Ethernet/HomePNA Controller

3.0 Function Description

3.1 USB Core and Interface

The USB core and interface contains an USB 2.0 transceiver, serial interface engine (SIE), USB bus protocol

handshaking block, USB standard command, vendor command registers, logic for supporting bulk transfer, and interrupt

transfer, etc. The USB interface is used to communicate with USB host controller and is compliant with USB

specification V1.1 and V2.0.

3.2 10/100 Ethernet PHY

The 10/100 Fast Ethernet PHY is compliant with IEEE 802.3 and IEEE 802.3u standards. It contains an on-chip crystal

oscillator, PLL-based clock multiplier, digital phase-locked loop for data/timing recovery. It provides over-sampling

mixed-signal transmit drivers complying with 10/100BASE-TX transmit wave shaping / slew rate control requirements.

It has robust mixed-signal loop adaptive equalizer for receiving signal recovery. It contains baseline wander corrective

block to compensate data dependent offset due to AC coupling transformers. It supports auto-negotiation and has

multi-function LED outputs.

3.3 MAC Core

The MAC core supports 802.3 and 802.3u MAC sub-layer functions, such as basic MAC frame receive and transmit,

CRC checking and generation, filtering, forwarding, flow-control in full-duplex mode, and collision-detection and

handling in half-duplex mode, etc. It provides a media-independent interface (MII) for implementing Fast Ethernet and

HomePNA functions.

The MAC core interfaces to both external MII interface I/O pins and MII interface of the embedded 10/100 Ethernet

PHY. The selection between the two MII interfaces is done via USB vendor command, Software PHY Select register.

Figure 3 shows the datapath diagram of 10/100 Ethernet PHY and MII interface to MAC core.

Figure 3: Internal Datapath Diagram of 10/100 Ethernet PHY and MII Interface

3.4 Station Management (STA)

The station management interface provides a simple, two-wire, serial interface to connect to a managed PHY device for

the purposes of controlling the PHY and gathering status from the PHY. The station management interface allows

MAC

Core

10/100

Ethernet PHY

RX

TX

MII Interface I/O:

RX_CLK, RXD [3:0], RX_DV,

RX_ER, COL, CRS

TX_CLK, TXD [3:0], TX_EN, TX_ER

RXIP/RXIN

TXOP/TXON