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AX88772 Datasheet(PDF) 8 Page - ASIX Electronics Corporation |
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AX88772 Datasheet(HTML) 8 Page - ASIX Electronics Corporation |
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8 / 43 page ![]() ASIX ELECTRONICS CORPORATION 8 AX88772 USB to 10/100 Fast Ethernet/HomePNA Controller ET_SPEED_LED O3 96 Ethernet speed LED indicator. This pin drives low when the Ethernet PHY is in 100BASE-TX mode and drives high when in 10BASE-T mode. Misc. Pins RESET_N I5/PU/S 12 Chip Reset Input. RESET_N pin is active low. When asserted, it puts the entire chip into reset state immediately. After completing reset, EEPROM data will be loaded automatically. EXTWAKEUP_N I5/PU/S 11 Remote-wakeup trigger from external pin. EXTWAKEUP_N should be asserted low for more than 2 cycles of 12MHz clock to be effective. For GPIO [2:0] B5/PD 1, 2, 3 General Purpose Input/ Output Pins. These pins are default as input pins after power-on reset. Please use GPIO0 for controlling the power down pin of external Ethernet Phy, if applicable. PHYRST_N O2 122 PHYRST_N is a tri-state output used for resetting external Ethernet PHY. This pin is default in tri-state after power-on reset. If external Ethernet PHY’s reset level is active low, connect this to PHY’s reset pin with a pulled-down resistor. If it’s active high, connect this to PHY with a pulled-up resistor. This way can make sure the external Ethernet PHY stays in reset state before software brings it out of reset. FORCEFS_N I3/PU 15 Force USB Full Speed (active low). For normal operation, user should keep this pin NC to enable USB High Speed handshaking process to decide the speed of USB bus. Setting this pin low sets the device to operate at Full speed mode only and disables Chirp K (HS handshaking process). LED O3 125 LED indicator: When USB bus is in Full speed, this pin drives high continuously. When USB bus is in High speed, this pin drives low continuously. This pin drives high and low in turn (blinking) to indicate TX data transfer going on whenever the host controller sends bulk out data transfer. USB_SPEED_LE D O3 126 USB bus speed LED indicator. When USB bus is in Full speed, this pin drives high continuously. When USB bus is in High speed, this pin drives low continuously. TESTSPEEDUP I3/PD 13 Test pin. For normal operation, user should keep this pin NC. HS_TEST_MODE I3/PD 42 Test pin. For normal operation, user should keep this pin NC. SCAN_TEST I3/PD 43 Test pin. For normal operation, user should keep this pin NC. SCAN_ENABLE I3/PD 44 Test pin. For normal operation, user should keep this pin NC. CLK60EXT I3/PD 45 Test pin. For normal operation, user should keep this pin NC. CLKSEL I3/PD 46 Test pin. For normal operation, user should keep this pin NC. DB [4:0] I2 101, 111, 112, 113, 114 Debug pins. For normal operation, user should set these pins low. On-chip Regulator Pins INT_REGULATO R_EN I 20 On-chip 3.3V to 2.5V voltage regulator enable. Connect this pin to VDDAH directly to enable on-chip regulator. Connect this pin to GNDAH to disable on-chip regulator. VDDAH P 22 3.3V Power supply to on-chip 3.3V to 2.5V voltage regulator. GNDAH P 23 Ground pin of on-chip 3.3V to 2.5V voltage regulator. V25 P 21 2.5V voltage output of on-chip 3.3V to 2.5V voltage regulator. Power and Ground Pins VDDK P 16, 24, 74, 99, 118 Digital Core Power. 2.5V. VDD2 P 80, 86, 123 Digital I/O Power. 2.5V. VDD3 P 8, 19, 41, 97, 128 Digital I/O Power. 3.3V. |
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