5

®

DAC7612

TIMING DIAGRAMS

LOGIC TRUTH TABLE

TIMING SPECIFICATIONS

TA = –40°C to +85°C and VDD = +5V.

SYMBOL

DESCRIPTION

MIN

TYP MAX UNITS

tCH

Clock Width HIGH

30

ns

tCL

Clock Width LOW

30

ns

tLDW

Load Pulse Width

20

ns

tDS

Data Setup

15

ns

tDH

Data Hold

15

ns

tLD1

Load Setup

15

ns

tLD2

Load Hold

10

ns

tCSS

Select

30

ns

tCSH

Deselect

20

ns

NOTE: All input control signals are specified with tR = tF = 5ns (10% to 90%

of +5V) and timed from a voltage level of 2.5V. These parameters are

guaranteed by design and are not subject to production testing.

SDI

CLK

t

CL

t

CH

t

DH

t

DS

SERIAL SHIFT

DAC

DAC

A1

A0

CLK

CS

LOADDACS

REGISTER

REGISTER A

REGISTER B

X

X

X

H

H

No Change

No Change

No Change

XX

↑

L

H

Shifts One Bit

No Change

No Change

LX

X

H(1)

L

No Change

Loads Serial

Loads Serial

Data Word

Data Word

H

L

X

H

L

No Change

Loads Serial

No Change

Data Word

H

H

X

H

L

No Change

No Change

Loads Serial

Data Word

↑ Positive Logic Transition; X = Don’t Care.

NOTE: (1) A HIGH value is suggested in order to avoid to “false clock” from

advancing the shift register and changing the DAC voltage.

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11 B12 B13

A1

A0

D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DATA INPUT TABLE

A1

(MSB)

(LSB)

SDI

CLK

CS

LOADDACS

A0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

t

CSS

t

LD1

t

LD2

t

CSH

LOADDACS

FS

ZS

V

OUT

t

LDW

t

S

±1 LSB

Error Band