TBD datasheet(54/80 Pages) FREESCALE

54 / 80 page

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

2.7.10.2

MII Transmit AC Timing Specifications

Table 46 provides the MII transmit AC timing specifications.

Figure 26 shows the MII transmit AC timing diagram.

2.7.10.3

MII Receive AC Timing Specifications

Table 47 provides the MII receive AC timing specifications.

Figure 25. MII Management Interface Timing

Table 46. MII Transmit AC Timing Specifications

Parameter/Condition

Symbol 1

Min

Max

Unit

TX_CLK duty cycle

tMTXH/tMTX

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

tMTKHDX

025

TX_CLK data clock rise

tMTXR

1.0

4.0

TX_CLK data clock fall

tMTXF

1.0

4.0

Notes:

Typical TX_CLK period (tMTX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.

Program GCR4 as 0x00030CC3.

Figure 26. MII Transmit AC Timing

Table 47. MII Receive AC Timing Specifications

Parameter/Condition

Symbol 1

Min

Max

Unit

RX_CLK duty cycle

tMRXH/tMRX

ETHMDC

ETHMDIO

(Input)

(Output)

tMDC

tMDCR

tMDCH

tMDDXKH

tMDDVKH

tMDKHDX

tMDHF

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

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