F0448 Datasheet

X0008129 Rev.1.4

Feb 17, 2021

Page 4

Figure 45. Input Return Loss for DSA1 Settings ....................................................................................................22

Figure 46. Output Return Loss for DSA1 Settings..................................................................................................22

Figure 47. Input Return Loss for DSA2 Settings ....................................................................................................22

Figure 48. Output Return Loss for DSA2 Settings..................................................................................................22

Figure 49. Reverse Isolation for DSA0 Settings .....................................................................................................23

Figure 50. Phase Deviation Between Adjacent States vs. DSA0 Setting (4GHz)..................................................23

Figure 51. Reverse Isolation for DSA1 Settings .....................................................................................................23

Figure 52. Phase Deviation Between Adjacent States vs. DSA1 Setting (4GHz)..................................................23

Figure 53. Reverse Isolation for DSA2 Settings .....................................................................................................23

Figure 54. Phase Deviation Between Adjacent States vs. DSA2 Setting (4GHz)..................................................23

Figure 55. DSA0 Absolute Attenuation Error (INL) at 4GHz ..................................................................................24

Figure 56. DSA0 Attenuator Step Error (DNL) at 4GHz ........................................................................................24

Figure 57. DSA1 Absolute Attenuation Error (INL) at 4GHz ..................................................................................24

Figure 58. DSA1 Attenuator Step Error (DNL) at 4GHz .........................................................................................24

Figure 59. DSA2 Absolute Attenuation Error (INL) at 4GHz ..................................................................................24

Figure 60. DSA2 Attenuator Step Error (DNL) at 4GHz .........................................................................................24

Figure 61. OIP3 vs. Frequency with POUT = 0dBm/Tone and Max Gain ................................................................25

Figure 62. OIP3 vs. Frequency with POUT = -10dBm/Tone and Max Gain .............................................................25

Figure 63. OIP3 vs. Frequency with POUT = -18dBm/Tone and DSA2 = 18dB .......................................................25

Figure 64. OIP3 vs. Frequency with POUT = 0dBm/Tone and DSA0 = 6dB ............................................................25

Figure 65. Output 1dB Compression ......................................................................................................................25

Figure 66. Stability Factor (K) .................................................................................................................................25

Figure 67. NF vs. Frequency as a Function of Temperature at Max Gain .............................................................26

Figure 68. Serial Register Data Flow Diagram (LSB Clock in First).......................................................................26

Figure 69. DSA1 Default Condition ........................................................................................................................27

Figure 70. Serial Timing Diagram ...........................................................................................................................28

Figure 71. Typical Application Schematic...............................................................................................................30

Figure 72. Evaluation Board – Top View ................................................................................................................31

Figure 73. Evaluation Board – Bottom View...........................................................................................................31

Figure 74. Evaluation Board Schematic .................................................................................................................32

Figure 75. Power Supply Connections – Top View ................................................................................................35

Figure 76. Power Supply Connections – Bottom View ...........................................................................................35

Figure 77. Two Ground Jumper Connections.........................................................................................................35

Figure 78. Two Standby Pin Connections ..............................................................................................................36

Figure 79. Two Jumpers for Serial Programming Connections..............................................................................37

Figure 80. Jumpers for Serial Programming Connections .....................................................................................38

Figure 81. Parallel Pin Connections .......................................................................................................................38

Figure 82. Control Pin Interface..............................................................................................................................39