F0448_V01 datasheet(9/43 Pages) RENESAS

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F0448 Datasheet

X0008129 Rev.1.4

Feb 17, 2021

Page 9

2.3

Electrical Characteristics (3.4GHz to 3.8GHz)

See F0448 Typical Application Circuit. VCC = +5V, TC = +25°C, fRF = 3.6GHz specifications apply when operated

as a dual-channel RF DVGA, maximum gain setting, POUT = 0dBm, ZRFI = ZRFO = 50

Ω, Evaluation Board (EVKit)

traces and connectors are de-embedded, unless otherwise stated. For BOM details of this specific band, see

Table 11.

Table 3. Electrical Characteristics (3.4GHz to 3.8GHz)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Logic Input High

VIH

Applies for all logic levels.

1.07 [1]

Logic Input Low

VIL

Applies for all logic levels.

0.63

Logic Current

(CLK, DATA, CSb_A, CSb_B,

VCTRL0_A, VCTRL1_A,

VCTRL2_A, VCTRL0_B,

VCTRL1_B, VCTRL2_B)

IIH, IIL

-5

μA

Logic Current for Standby

(STBY_A, STBY_B) [2]

IIH-SB, IIL-SB

5V logic

-5

127

μA

3.3V logic

-5

1.8V logic

-5

Supply Current

ICC_2

Both channels on

220

270

ICC_1

One channel on

110

142

ICC_STBY

Standby Mode

Startup Time

tSTART

50% of STBY going LOW to

Gain within ± 1dB with no

attenuation.

DSA0 Adjustment Range

AADJ0

6dB step size

DSA1 Adjustment Range

AADJ1

1dB step size

DSA2 Adjustment Range

AADJ2

6dB step size

Maximum Attenuation Glitch

ATTNG

DSA0 Gain Settling Time

tDSA0_1

50% CTRL to within 0.1dB final

value, 0dB state to 6dB state

tDSA0_2

50% CTRL to within 0.1dB final

value, 6dB state to 0dB state

DSA1 Gain Settling Time

tDSA1

50% of CSb to within 0.1dB final

value

300

DSA2 Gain Settling Time

tDSA2_1

50% CTRL to within 0.1dB final

value, 0dB state to 18dB state

tDSA2_2

50% CTRL to within 0.1dB final

value, 18dB state to 0dB state

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