LM2512A

SNLS269B – AUGUST 2007 – REVISED MAY 2013

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Table 5. LM2512A SPI Registers

Name

Addres

Type(1) Description

Default

s

Command

0x00

R/W

Bit 0 = LUT Enable

00’h

0’b = LUT Disabled, 1’b = LUT Enabled

Bit 4 = Special Register Access

0’b = SRA Locked, 1’b = SRA Unlocked

For access to Registers 0x01, 0x08, 0x09, 0x0A, the Special Register Access bit

must be unlocked. Must write all 8 bits.

Configuration(2)

0x01

R/W

Bit 4 = MPL Edge Rate

00’h

0’b = normal edge, 1’b = slow edge

All other bits reserved, must be written as 0s.

Red RAM Address

0x02

R/W

Red Address

00’h

Red RAM Data

0x03

R/W

Red Data

XX’h

Green RAM Address

0x04

R/W

Green Address

00’h

Green RAM Data

0x05

R/W

Green Data

XX’h

Blue RAM Address

0x06

R/W

Blue Address

00’h

Blue RAM Data

0x07

R/W

Blue Data

XX’h

Dither Configuration1

0x08

R/W

Bit 0 - Dither Bypass

61’h

(2)

1’b = Bypass Dither, 0’b = Dither ON

Bit 1 - DE INV

1’b = Active Low DE, 0’b = Active High DE

Does not alter DE signal, dither block input only.

Bit 2 - VS INV

1’b = Active Low VS signal, 0’b = Active High VS signal.

Does not alter VS signal, dither block input only.

Bit 3 - Reserved

Bit 4 - Tempen0

1’b = Transposed Dither Pattern,

0’b = Even and odd frames use same dither pattern

Bit 5 - Tempen1

1’b = Temporal Dithering is Enabled, 0’b = Disabled

Bit 6 - Dith3 - Dither Amplitude

1’b = set to 3 bits, 0’b = set to 4 bits

Bit 7 - Reserved

Dither Configuration2

0x09

R/W

Dither Parameter

67’h

(2)

Reserved, Default value recommended.

Lane Scale

0x0A

W

Bit[2:0]

02’h

(2) (3)

000’b = Reserved

010’b = 2 MD Lanes (Default)

100’b = 3 MD Lanes

all others= Reserved

Reserved

0x0B-

na

Reserved

(4)

0x15

Device Select

0x16

R/W

0xFF’h enables LM2512A SPI

00’h

(Unlock/Lock)

All other values disables LM2512A SPI (0x00 to 0xFE)

Reserved

0x17-

na

Reserved

(4)

0x7F

(1)

If a WRITE is done to a reserved bits, data should be all 0’s. If a READ is done to a reserved location, either 1’s or 0’s may be returned.

Mask reserved data bits.

(2)

This register must be unlocked first through bit 4 of register 0.

(3)

WRITE ONLY Register, read of this register is not supported.

(4)

DO NOT write to Reserved Registers.

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