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Ball A1

LM2512A

www.ti.com

SNLS269B – AUGUST 2007 – REVISED MAY 2013

The MPL lines should generally run together to minimize any trace length differences (skew). For impedance

control and also noise isolation (crosstalk), guard ground traces are recommended in between the signals.

Commonly a Ground-Signal-Ground (GSGSGSG) layout is used. Locate fast edge rate and large swing signals

further away to also minimize any coupling (unwanted crosstalk). In a stacked flex interconnect, crosstalk also

needs to be taken into account in the above and below layers (vertical direction). To minimize any coupling

locate MPL traces next to a ground layer. Power rails also tend to generate less noise than LVCMOS so they are

also good candidates for use as isolation and separation.

The interconnect from the SER to the DES typically acts like a transmission line. Thus impedance control and

ground returns are an important part of system design. Impedance should be in the 50 to 100 Ohm nominal

range for the LM2512A. Testing has been done with cables ranging from 40 to 110 Ohms without error (BER

Testing). To obtain the impedance, adjacent grounds are typically required (1 layer flex), or a ground shield /

layer. Total interconnect length is intended to be in the 20cm range, however 30cm is possible at lower data

rates. Skew should be less than 500ps to maximize timing margins.

GROUNDING

While the LM2512A employs three separate types of ground pins, these are intended to be connected together

to a common ground plane. The separate ground pins help to isolate switching currents from different sections of

the integrated circuit (IC). Also required is a nearby signal return (ground) for the MPL signals. These should be

provided next to the MPL signals, as that will create the smallest current loop area. The grounds are also useful

for noise isolation and impedance control.

PCB RECOMMENDATIONS

General guidelines for the PCB design:

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Floor plan, locate MPL SER near the connector to limit chance of cross talk to high speed serial signals.

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Route serial traces together, minimize the number of layer changes to reduce loading.

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Use ground lines as guards to minimize any noise coupling (specifies distance).

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Avoid parallel runs with fast edge, large LVCMOS swings.

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Also use a GSGSG pinout in connectors (Board to Board or ZIF).

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DES device - follow similar guidelines.

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Bypass the device with MLC surface mount devices and thinly separated power and ground planes with low

inductance feeds.

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High current returns should have a separate path with a width proportional to the amount of current carried to

minimize any resulting IR effects.

CONNECTION DIAGRAM 49 NFBGA PACKAGE

Figure 21. TOP VIEW

(not to scale)

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