1

bit7

1

bit6

1

bit5

1

bit4

1

bit3

1

bit2

VF1

bit1

VF0

bit0

MSB

LSB

VF Monitor Delay Register

Register Address: 0x60

1

bit7

1

bit6

1

bit5

1

bit4

0

bit3

0

bit2

RS1

bit1

RS0

bit0

MSB

LSB

Ramp Step Time Register

Register Address: 0x20

LM2756

SNVS504C – JULY 2007 – REVISED MAY 2013

www.ti.com

Table 1. Brightness Level Control Table (GroupA) (continued)

Brightness Code (hex)

Perceived Brightness Level (%)

0B

3.75

0C

4.375

0D

5.25

0E

6.25

0F

7.5

10

8.75

11

10

12

12.5

13

15

14

16.875

15

18.75

16

22.5

17

26.25

18

31.25

19

37.5

1A

43.75

1B

52.5

1C

61.25

1D

70

1E

87.5

1F

100

GroupB and GroupC Brightness Levels (% of Full-Scale) = 10%, 20%, 30%, 40%, 50%, 60%, 70%, 100%

Figure 24. Ramp Step Time Register Description

Internal Hex Address: 20h

NOTE

RS1-RS0: Sets Brightness Ramp Step Time. The Brightness ramp settings only affect

GroupA current sinks. ('00' = 100µs, '01' = 25ms, '10' = 50ms, '11' = 100ms).

Figure 25. VF Monitor Delay Register Description

Internal Hex Address: 60h

NOTE

VF1-VF0: Sets the Gain Transition Delay Time. The VF Monitor Delay can be set to four

different delay times. ('00' (Default) = 3-6msec., '01' = 1.5-3msec., '10' = 0.4-0.8msec., '11'

= 60-90µsec.).

14

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