SDA

SCL

S

P

START condition

STO

P condition

TI Confidential - NDA Restrictions

LM49151

www.ti.com

SNAS482F – MARCH 2009 – REVISED MARCH 2013

APPLICATION INFORMATION

WRITE-ONLY I

2C COMPATIBLE INTERFACE

The LM49151 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and

a serial clock (SCL). The SCL and SDA lines are uni-directional write only interface. The LM49151 and the

master can communicate at clock rates up to 400kHz. Figure 51 shows the I2C interface timing diagram. Data on

the SDA line must be stable during the HIGH period of SCL. The LM49151 is a slave-only device, reliant upon

the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a

STOP condition (Figure 52). Each data word and device address transmitted over the bus is 8 bits long and is

always followed by an acknowledge pulse (Figure 53). The LM49151 device address is 11111000.

I

2C BUS FORMAT

The bus format for the I2C interface is shown in Figure 53. The bus format diagram is broken up into six major

sections: The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start

signal will alert all devices attached to the I2C bus to check the incoming address against their own address. The

8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.

Each address bit must be stable while the clock level is HIGH. After the last bit of the address bit is sent, the

master releases the data line HIGH (through a pull-up resistor). Then the master sends an acknowledge clock

pulse. If the LM49151 has received the address correctly, then it holds the data line LOW during the clock pulse.

If the data line is not held LOW during the acknowledge clock pulse, then the master should abort the rest of the

data transfer to the LM49151. The 8 bits of data are sent next, most significant bit first. Each data bit should be

valid while the clock level is stable HIGH. After the data byte is sent, the master must check for another

acknowledge to see if the LM49151 received the data. If the master has more data bytes to send to the

LM49151, then the master can repeat the previous two steps until all data bytes have been sent. The "stop"

signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH. The data line

should be held HIGH when not in use.

I

2C INTERFACE POWER SUPPLY PIN (I2CV

DD)

The LM49151's I2C interface is powered up through the I2CVDD pin. The LM49151 I

2C interface operates at a

voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This

is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is

operating at a lower supply voltage than the main battery of a portable system.

Figure 51. I2C Timing Diagram

Figure 52. Start and Stop Diagram

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