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LM5025BMTC/NOPB Datasheet(PDF) 6 Page - Texas Instruments |
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LM5025BMTC/NOPB Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 25 page ![]() LM5025B SNVS354B – JULY 2005 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (1) (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 27.4kΩ) unless otherwise stated Symbol Parameter Conditions Min Typ Max Units Current Limit CS1 Prop CS1 Delay to Output CS1 Step from 0 to 0.4V 40 ns Time to onset of OUT Transition (90%) Cgate = 0 CS2 Prop CS2 Delay to Output CS2 Step from 0 to 0.6V 50 ns Time to onset of OUT Transition (90%) Cgate = 0 Cycle by Cycle Threshold 0.22 0.25 0.28 V Voltage (CS1) Cycle Skip Threshold Resets SS capacitor; auto 0.45 0.5 0.55 V Voltage (CS2) restart Leading Edge Blanking 50 ns Time (CS1) CS1 Sink Impedance CS1 = 0.2V 30 50 Ω (clocked) CS1 Sink Impedance CS1 = 0.3V 55 95 Ω (Post Fault Discharge) CS2 Sink Impedance CS2 = 0.6V 55 95 Ω (Post Fault Discharge) CS1 and CS2 Leakage CS = CS Threshold - 100mV 1 µA Current Soft-Start Soft-start Current Source 17 22 27 µA Normal Soft-start Current Source 0.5 1 1.5 µA following a CS2 event Oscillator Frequency1 TA = 25°C 180 220 200 kHz TJ = Tlow to Thigh 175 225 Frequency2 RT = 13.3 k Ω TJ = Tlow to Thigh 360 400 440 kHz TJ = 0°C to 125°C 364 436 Sync threshold 2 V Min Sync Pulse Width 100 ns Sync Frequency Range 160 kHz PWM Comparator Delay to Output COMP step 5V to 0V 40 ns Time to onset of OUT_A transition low Maximum Duty Cycle 1 Measured at OUT_A 73 % Maximum Duty Cycle 2 Measured at OUT_A; 66 71 75 RT = 13.3K COMP to PWM Offset 0.75 1 1.15 V COMP Input Current COMP = 4V, SS open 50 80 µA Volt x Second Clamp Ramp Clamp Level Delta RAMP measured from 2.4 2.5 2.6 V onset of OUT_A to Ramp peak. COMP = 5V 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5025B |
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