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LP3923TL/NOPB Datasheet(PDF) 14 Page - Texas Instruments |
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LP3923TL/NOPB Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 37 page  LP3923 SNVS567B – APRIL 2010 – REVISED MAY 2013 www.ti.com POWER UP AND POWER DOWN SEQUENCES (1) CHG_IN is edge sensitive and HF_PWR is level sensitive at startup in STANDBY mode and level sensitive in POWER-ON-RESET mode. (2) PWR_ON is level sensitive at startup. PS_HOLD must be asserted before PWR_ON goes LOW to keep PMU powered. PWR_ON input is not monitored after PMU is powered up (PS_HOLD asserted). (3) PON_N is a direct inversion of PWR_ON input when LDO3 is powered up (no power-on switch debouncing on PON_N output). (4) The input signal which activates Power Up sequence (either PWR_ON or CHG_IN or HF_PWR) must be on when PS_HOLD is asserted. (5) Time delay between the PS_HOLD going low and the start of Power Down sequence depends on PS_HOLD_DELAY setting (0=35ms, 1=350ms) (typ.). Figure 1. Power Up and Power Down Timing Diagram 14 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LP3923 |
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