PCM1740ESLASH2K datasheet(16/26 Pages) TI2

16 / 26 page

PCM1740

SBAS128B

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Data transfer begins with a Start condition, and is immedi-

ately followed by the Slave address and Read / Write bit. The

Read/ Write bit is set to ‘0’ for the PCM1740, in order to

write data to the control register specified by the sub-

address. This is followed by an acknowledgment from the

PCM1740, the sub-address (that is, the control register

address), another acknowledgment from the PCM1740, the

control register data, and another acknowledgment from the

PCM1740. What happens after this depends on if the user

wants to continue writing additional control registers, or if

they want to terminate the data transfer. If the user wants to

continue, the acknowledgment is followed by a Start condi-

tion for the next write sequence. If the user decides to

terminate the data transfer, then a Stop condition is gener-

ated by the Master.

The I2C-Bus specification defines timing requirements for

devices connected to the bus. Timing requirements for the

PCM1740 are shown in Figure 15.

Reference

For additional information regarding the I2C-Bus, please

refer to the I2C-Bus Specification available online from

NXP Semiconductors.

FIGURE 15. I2C Bus Timing.

SDA

SCL

S: START condition

Sr: repeated START condition

P: STOP condition

HD; STA

HD; DAT

HIGH

SU; STA

SU; STO

HD; STA

LOW

SU, DAT

BUF

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

fSCL

SCL Clock Frequency

100

kHz

tHD; STA

Hold time (repeated) START condition,

4.0

µs

after this period, the first clock pulse is

generated

tLOW

LOW period of the SCL clock

4.7

µs

tHIGH

HIGH period of the SCL clock

4.0

µs

tSU:STA

Set-up time for a repeated START condition

4.7

µs

tHD;DAT

Data hold time for I2C-BUS devices

3.45(2)

µs

tSU;DAT

Data set-up time

250

Rise time of both SDA and SCL signals

1000

Fall time of both SDA and SCL signals

300

tSU;STO

Set-up time for STOP condition

4.0

µs

tBUF

Bus free time between a STOP and START

4.7

µs

condition

Capacitive load for each bus line

400

VNL

Noise margin at the LOW level for each

0.1 VDD

connected device (including hysteresis)

VNH

Noise margin at the HIGH level for each

0.2 VDD

connected device (including hysteresis)

PCM1740E/2K Datasheet(PDF) 16 Page - Texas Instruments

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