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PCM1801U/2K Datasheet(PDF) 17 Page - Texas Instruments

Part # PCM1801U/2K
Description  SINGLE-ENDED ANALOG-INPUT 16-BIT STEREO ANALOG-TO-DIGITAL CONVERTER
PDF  25 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

PCM1801U/2K Datasheet(HTML) 17 Page - Texas Instruments

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DOUT PIN
FMT PIN
SYSTEM CLOCK
TYPICAL CIRCUIT CONNECTION DIAGRAM
S0013-01
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Format
Latch Enable
Data Out
+
Pin Program
or Control
Audio
Data
Processor
Lch In
+5 V
C4(2)
VREF1
VREF2
AGND
VCC
FMT
BYPAS
DOUT
VINL
VINR
DGND
VDD
SCKI
BCK
LRCK
0 V
Bypass
+
C6(3)
+
C5(3)
Data Clock
System Clock
C3(2)
+
Rch In
C1(1)
C2(1)
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
The DOUT pin has a large load-drive capability, but locating a buffer near the PCM1801 and minimizing load
capacitance is recommended in order to minimize the digital-analog crosstalk and maximize the dynamic
performance of the ADC.
In general, the FMT pin is used for audio data format selection by tying up DGND or VDD in accordance with
interface requirements. If the application system cannot ensure an effective system clock prior to power up of
the PCM1801 when I2S format is required, then the FMT pin must be set HIGH after the power-on reset
sequence. This input control can be accomplished easily by connecting a C-R delay circuit with a delay time
greater than 1 ms to the FMT pin.
The quality of the system clock can influence dynamic performance in the PCM1801. The duty cycle, jitter, and
threshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part,
the system clock, bit clock (BCK), and word clock (LRCK) should also be supplied simultaneously. Failure to
supply the audio clocks results in a power dissipation increase of up to three times normal dissipation and may
degrade long-term reliability if the maximum power dissipation limit is exceeded.
Figure 28 is a typical connection diagram illustrating a circuit for which the input HPF cutoff frequency is about
5 Hz.
(1)
C1 and C2: A 1-
μF capacitor gives a 5.3-Hz (τ = 1 μF * 30 k
Ω) cutoff frequency for the input HPF in normal operation
and requires a power-on setting time of 30 ms at power up.
(2)
C3 and C4: Bypass capacitors, 0.1-
μF ceramic and 10-μF tantalum or aluminum electrolytic, depending on layout
and power supply
(3)
C5 and C6: 4.7-
μF tantalum or aluminum electrolytic capacitors
Figure 28. Typical Circuit Connection
17
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