SII3531A datasheet(49/81 Pages) SILICONIMAGE

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PCI Express to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

SiI-DS-0208-C

6.1.14 MSI Capability

Address Offset: 5CH

Access Type: Read/Write

Reset Value: 0x0080_7005

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Reserved

Multiple

Message

Enable

Multiple

Message

Capable

Next Capability Pointer

Capability ID

This register defines the MSI Capability Message Control. The register bits are defined below.

•

Bit [31:24]: Reserved (R) – This bit field is reserved and returns zeros on a read.

•

Bit [23]: 64-bit Addr (R) – 64-bit Address Capable. This bit is hardwired to 1.

•

Bit [22:20]: Multiple Message Enable (R/W) – This bit field defaults to 000B.

•

Bit [19:17]: Multiple Message Capable (R) – This bit field is hardwired to 000B.

•

Bit [16]: MSI Enable (R/W) – This bit is set to enable Message Signaled Interrupts.

•

Bit [15:08]: Next Capability Pointer (R) –Next Capability Pointer. This bit field is hardwired to 70H to point to the

rd Capabilities register, the PCI Express Capability.

•

Bit [07:00]: Capability ID (R) – This bit field is hardwired to 05H to indicate that this is a MSI Capability.

6.1.15 Message Address

Address Offset: 60H-67H

Access Type: Read/Write

Reset Value: 0x0000_0000_0000_0000

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Message Address Upper

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Message Address

This register specifies the memory address for an MSI memory write transaction. The memory address must be of a Dword

(bits 1:0 must be 0).

6.1.16 MSI Message Data

Address Offset: 68H

Access Type: Read/Write

Reset Value: 0x0000_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Reserved

Message Data

This register specifies the MSI Message Data. The register bits are defined below.

•

Bit [31:16]: Reserved (R) – This bit field is reserved and returns zeros on a read.

•

Bit [15:00]:

Message Data (R/W) – This bit field specifies the Message Data for an MSI memory write

transaction.

SII3531A Datasheet(PDF) 49 Page - Silicon image

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