ST72F324LJ2T5 datasheet(150/154 Pages) STMICROELECTRONICS

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ST72324Lxx

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15.1.6 SCI Wrong Break duration

Description

A single break character is sent by setting and re-

setting the SBK bit in the SCICR2 register. In

some cases, the break character may have a long-

er duration than expected:

- 20 bits instead of 10 bits if M=0

- 22 bits instead of 11 bits if M=1.

In the same way, as long as the SBK bit is set,

break characters are sent to the TDO pin. This

may lead to generate one break more than expect-

ed.

Occurrence

The occurrence of the problem is random and pro-

portional to the baudrate. With a transmit frequen-

cy of 19200 baud (fCPU=8 MHz and SCI-

BRR=0xC9), the wrong break duration occurrence

is around 1%.

Workaround

If this wrong duration is not compliant with the

communication protocol in the application, soft-

ware can request that an Idle line be generated

before the break character. In this case, the break

duration is always correct assuming the applica-

tion is not doing anything between the idle and the

break. This can be ensured by temporarily disa-

bling interrupts.

The exact sequence is:

- Disable interrupts

- Reset and Set TE (IDLE request)

- Set and Reset SBK (Break Request)

- Re-enable interrupts

15.1.7 External interrupt missed

To avoid any risk of generating a parasitic inter-

rupt, the edge detector is automatically disabled

for one clock cycle during an access to either DDR

and OR. Any input signal edge during this period

will not be detected and will not generate an inter-

rupt.

This case can typically occur if the application re-

freshes the port configuration registers at intervals

during runtime.

Workaround

The workaround is based on software checking

the level on the interrupt pin before and after writ-

ing to the PxOR or PxDDR registers. If there is a

level change (depending on the sensitivity pro-

grammed for this pin) the interrupt routine is in-

voked using the call instruction with three extra

PUSH instructions before executing the interrupt

routine (this is to make the call compatible with the

IRET instruction at the end of the interrupt service

routine).

But detection of the level change does not make

sure that edge occurs during the critical 1 cycle du-

ration and the interrupt has been missed. This may

lead to occurrence of same interrupt twice (one

hardware and another with software call).

To avoid this, a semaphore is set to '1' before

checking the level change. The semaphore is

changed to level '0' inside the interrupt routine.

When a level change is detected, the semaphore

status is checked and if it is '1' this means that the

last interrupt has been missed. In this case, the in-

terrupt routine is invoked with the call instruction.

There is another possible case that is, if writing to

PxOR or PxDDR is done with global interrupts dis-

abled (interrupt mask bit set). In this case, the

semaphore is changed to '1' when the level

change is detected. Detecting a missed interrupt is

done after the global interrupts are enabled (inter-

rupt mask bit reset) and by checking the status of

the semaphore. If it is '1' this means that the last

interrupt was missed and the interrupt routine is in-

voked with the call instruction.

To implement the workaround, the following soft-

ware sequence is to be followed for writing into the

PxOR/PxDDR registers. The example is for Port

PF1 with falling edge interrupt sensitivity. The soft-

ware sequence is given for both cases (global in-

terrupt disabled/enabled).

Case 1: Writing to PxOR or PxDDR with Global In-

terrupts Enabled:

LD A,#01

LD sema,A; set the semaphore to '1'

LD A,PFDR

AND A,#02

LD X,A; store the level before writing to PxOR/

PxDDR

LD A,#$90

LD PFDDR,A ; Write to PFDDR

LD A,#$ff

LD PFOR,A ; Write to PFOR

LD A,PFDR

AND A,#02

LD Y,A; store the level after writing to PxOR/PxD-

LD A,X; check for falling edge

cp A,#02

jrne OUT

TNZ Y

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