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ST72F324LJ2T5 Datasheet(PDF) 151 Page - STMicroelectronics

Part # ST72F324LJ2T5
Description  3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface
PDF  154 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72F324LJ2T5 Datasheet(HTML) 151 Page - STMicroelectronics

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jrne OUT
LD A,sema ; check the semaphore status if edge is
detected
CP A,#01
jrne OUT
call call_routine ; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt ; entry to interrupt routine
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with Global In-
terrupts Disabled:
SIM ; set the interrupt mask
LD A,PFDR
AND A,#$02
LD X,A ; store the level before writing to PxOR/
PxDDR
LD A,#$90
LD PFDDR,A ; Write into PFDDR
LD A,#$ff
LD PFOR,A ; Write to PFOR
LD A,PFDR
AND A,#$02
LD Y,A ; store the level after writing to PxOR/PxD-
DR
LD A,X ; check for falling edge
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A ; set the semaphore to '1' if edge is de-
tected
RIM ; reset the interrupt mask
LD A,sema ; check the semaphore status
CP A,#$01
jrne OUT
call call_routine ; call the interrupt routine
RIM
OUT:RIM
JP while_loop
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt ; entry to interrupt routine
LD A,#$00
LD sema,A
IRET
15.2 ROM DEVICES ONLY
15.2.1 I/O Port A and F Configuration
When using an external quartz crystal or ceramic
resonator, the fOSC2 clock may be disturbed be-
cause the device goes into reserved mode control-
led by Port A and F.
This happens with either one of the following con-
figurations:
PA3=0, PF4=1, PF1=0 when the PLL option is dis-
abled and PF0 is toggling
PA3=0, PF4=1, PF1=0, PF0=1 when the PLL op-
tion is enabled
This is detailed in the following table:
As a consequence, for cycle-accurate operations,
these configurations are prohibited in either input
or output mode.
Workaround:
To avoid this occurring, it is recommended to con-
nect one of these pins to GND (PF4 or PF0) or
VDD (PA3 or PF1).
PLL PA3 PF4 PF1 PF0 Clock Disturbance
OFF
0
1
0
Tog-
gling
Max. 2 clock cycles
lost at each rising or
falling edge of PF0
ON
0
1
0
1
Max. 1 clock cycle
lost out of every 16
1



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