6.6 PLL/VCO/Clock Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; Reference clock input frequency

491.52MHz (unless otherwise noted), fDAC = fVCO, fOUT = fDAC/4, normalized to fVCO.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fVCO1

VCO1 min frequency

7.2

GHz

VCO1 max frequency

7.68

GHz

fVCO2

VCO2 min frequency

8.8

GHz

VCO2 max frequency

9.1

GHz

fVCO3

VCO3 min frequency

9.7

GHz

VCO3 max frequency

10.24

GHz

fVCO4

VCO4 min frequency

11.6

GHz

VCO4 max frequency

12.08

GHz

DIVDAC

DAC sample rate divider

1, 2 or 3

DIVFBAD

C

ADC sample rate divider from DAC

sample rate

1, 2, 3, 4,

6 or 8

DIVRXAD

C

ADC sample rate divider

1, 2, 3, 4,

6 or 8

PNVCO

Closed Loop Phase Noise FPLL =

11.79848 GHz FREF=491.52MHz

600kHz

-113

dBc/Hz

800kHz

-116

dBc/Hz

1MHz

-119

dBc/Hz

1.8MHz

-125

dBc/Hz

5MHz

-133

dBc/Hz

50MHz

–141

dBc/Hz

Closed Loop Phase Noise FPLL=8.84736

GHz FREF=491.52MHz

600kHz

-114

dBc/Hz

800kHz

–118

dBc/Hz

1MHz

–120

dBc/Hz

1.8MHz

–127

dBc/Hz

5MHz

–135

dBc/Hz

50MHz

–142

dBc/Hz

Closed Loop Phase Noise FPLL= 9.8403

GHz FREF=491.52MHz

600kHz

–113

dBc/Hz

800kHz

–116

dBc/Hz

1MHz

–119

dBc/Hz

1.8MHz

–125

dBc/Hz

5MHz

–134

dBc/Hz

50MHz

–140

dBc/Hz

Closed Loop Phase Noise FPLL=

7.86432GHz FREF=491.52MHz

600kHz

–116

dBc/Hz

800kHz

–119

dBc/Hz

1MHz

–122

dBc/Hz

1.8MHz

–127

dBc/Hz

5MHz

–136

dBc/Hz

50MHz

–143

dBc/Hz

Frms

Clock PLL integrated phase error(1)

fPLL=11.79848 GHz, [1KHz, 100MHz]

-43.4

dBc/Hz

fPLL=8.8536 GHz, [1KHz, 100MHz]

-47.6

dBc/Hz

fPLL=9.8304 GHz, [1KHz, 100MHz]

-46.2

dBc/Hz

fPFD

PFD frequency

100

500

MHz

PNpll_flat Normalized PLL flat Noise

fVCO = 11796.48MHz

–226.5

dBc/Hz

FREF

Input Clock frequency

0.1

12

GHz

VSS

Input Clock level

0.6

1.8

Vppdiff

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AFE7954

SBASAO7 – JULY 2023

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