CC2550-RTY1 datasheet(22/62 Pages) TI2

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CC2550

SWRS039B

Page 22 of 58

13.3

Packet Handling in Transmit Mode

The payload that is to be transmitted must be

written into the TX FIFO. The first byte written

must be the length byte when variable packet

length is enabled. The length byte has a value

equal to the payload of the packet (including

the optional address byte). If fixed packet

length is enabled, then the first byte written to

the TX FIFO is interpreted as the destination

address, if this feature is enabled in the device

that receives the packet.

The modulator will first send the programmed

number of preamble bytes. If data is available

in the TX FIFO, the modulator will send the

two-byte (optionally 4-byte) sync word and

then the payload in the TX FIFO. If CRC is

enabled, the checksum is calculated over all

the data pulled from the TX FIFO and the

result is sent as two extra bytes at the end of

the payload data. If the TX FIFO runs empty

before

the

complete

packet

has

been

transmitted,

the

radio

will

enter

TXFIFO_UNDERFLOW state. The only way to

exit this state is by issuing an SFTX strobe.

Writing to the TX FIFO after it has underflowed

will not restart TX mode.

If whitening is enabled, everything following

the sync words will be whitened. This is done

before the optional FEC/Interleaver stage.

Whitening

enabled

setting

PKTCTRL0.WHITE_DATA

=1.

If FEC/Interleaving is enabled, everything

following the sync words will be scrambled by

the interleaver, and FEC encoded before being

modulated. FEC is enabled by setting

MDMCFG.FEC_EN

=1.

13.4

Packet Handling in Firmware

When implementing a packet oriented radio

protocol in firmware, the MCU needs to know

when

packet

has

been

transmitted.

Additionally, for packets longer than 64 bytes

the TX FIFO needs to be refilled while in TX.

This means that the MCU needs to know the

number of bytes that can be written to TX

FIFO. There are two possible solutions to get

the necessary status information:

a) Interrupt driven solution

It is possible to use one of the GDO pins to give

an interrupt when a sync word has been

transmitted and/or when a complete packet

has been transmitted (IOCFGx=0x06). In

addition, there are 2 configurations for the

IOCFGx

TX FIFO (IOCFGx=0x02 and IOCFG=0x03)

that can be used as interrupt sources to

provide information on how many bytes are in

the TX FIFO. See Table 22.

b) SPI polling

The PKTSTATUS register can be polled at a

given rate to get information about the current

GDO0

value. The TXBYTES register can be

polled at a given rate to get information about

the number of bytes in the TX FIFO.

Alternatively, the number of bytes in the TX

FIFO can be read from the chip status byte

returned on the MISO line each time a header

byte, data byte, or command strobe is sent on

the SPI bus. This only valid when R/W = 0.

As explained in Section 10.3 and the

CC2550

Errata Notes [1], when using SPI polling there

is a small, but finite, probability that a single

read from registers PKTSTATUS and TXBYTES

is being corrupt. The same is the case when

reading the chip status byte. It is therefore

recommended to employ an interrupt driven

solution.

Refer to the TI website for SW examples ([5]

and [6]).

Modulation Formats

CC2550 supports amplitude, frequency and

phase shift modulation formats. The desired

modulation

format

set

the

MDMCFG2.MOD_FORMAT

Optionally, the data stream can be Manchester

coded by the modulator. This option is enabled

setting

MDMCFG2.MANCHESTER_EN

=1.

Manchester encoding is not supported at the

same time as using the FEC/Interleaver

option.

CC2550-RTY1 Datasheet(PDF) 22 Page - Texas Instruments

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