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SNLS124A Datasheet(PDF) 16 Page - Texas Instruments

Part # SNLS124A
Description  DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
PDF  30 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

SNLS124A Datasheet(HTML) 16 Page - Texas Instruments

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DS90C383SLC SLC64A (FBGA) Package Pin Description — FPD Link
Transmitter (Continued)
By Pin
By Pin Type
G7
TxIN21
I
C7
PLL VCC
P
G8
TxIN23
I
E1
VCC
P
H1
TxIN9
I
E6
VCC
P
H2
VCC
P
H2
VCC
P
H3
TxIN11
I
B8
NC
H4
TxIN14
I
C2
NC
H5
TxIN15
I
C3
NC
H6
TxIN18
I
F2
NC
H7
TxIN19
I
F3
NC
H8
TxIN20
I
F6
NC
G : Ground
I : Input
O : Output
P : Power
NC : No Connect
DS90CF384 MTD56 TSSOP Package Pin Description — FPD Link Receiver
Pin Name
I/O
No.
Description
RxIN+
I
4
Positive LVDS differentiaI data inputs.
RxIN−
I
4
Negative LVDS differential data inputs.
RxOUT
O
28
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
I
1
Positive LVDS differential clock input.
RxCLK IN−
I
1
Negative LVDS differential clock input.
FPSHIFT OUT
O
1
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
PWR DOWN
I
1
TTL level input. When asserted (low input) the receiver outputs are low.
V
CC
I
4
Power supply pins for TTL outputs.
GND
I
5
Ground pins for TTL outputs.
PLL V
CC
I
1
Power supply for PLL.
PLL GND
I
2
Ground pin for PLL.
LVDS V
CC
I
1
Power supply pin for LVDS inputs.
LVDS GND
I
3
Ground pins for LVDS inputs.
DS90CF384 64 ball FBGA Package Pin Description — FPD Link Receiver
Pin Name
I/O
No.
Description
RxIN+
I
4
Positive LVDS differentiaI data inputs.
RxIN−
I
4
Negative LVDS differential data inputs.
RxOUT
O
28
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
I
1
Positive LVDS differential clock input.
RxCLK IN−
I
1
Negative LVDS differential clock input.
FPSHIFT OUT
O
1
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
PWR DOWN
I
1
TTL level input. When asserted (low input) the receiver outputs are low.
V
CC
I
4
Power supply pins for TTL outputs.
GND
I
5
Ground pins for TTL outputs.
PLL V
CC
I
1
Power supply for PLL.
PLL GND
I
2
Ground pin for PLL.
LVDS V
CC
I
2
Power supply pin for LVDS inputs.
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