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SNLS124A Datasheet(PDF) 13 Page - Texas Instruments

Part # SNLS124A
Description  DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
PDF  30 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

SNLS124A Datasheet(HTML) 13 Page - Texas Instruments

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AC Timing Diagrams (Continued)
Applications Information
The DS90C383 and DS90CF384 are backward compatible
with the existing 5V FPD Link transmitter/receiver pair
(DS90CR583, DS90CR584, DS90CF583 and DS90CF584).
To upgrade from a 5V to a 3.3V system the following must be
addressed:
1.
Change 5V power supply to 3.3V. Provide this supply to
the V
CC, LVDS VCC and PLL VCC of both the transmitter
and receiver devices. This change may enable the re-
moval of a 5V supply from the system, and power may
be supplied from an existing 3V power source.
2.
The DS90C383 (transmitter) incorporates a rise/fall
strobe select pin. This select function is on pin 17,
formerly a V
CC connection on the 5V products. When the
rise/fall strobe select pin is connected to V
CC, the part is
configured with a rising edge strobe. In a system cur-
rently using a 5V rising edge strobe transmitter
(DS90CR583), no layout changes are required to ac-
commodate the new rise/fall select pin on the 3.3V
transmitter. The V
CC signal may remain at pin 17, and
the device will be configured with a rising edge strobe.
When converting from a 5V falling edge transmitter
(DS90CF583) to the 3V transmitter a minimal board
layout change is necessary. The 3.3V transmitter will
not be configured with a falling edge strobe if V
CC re-
mains connected to the select pin. To guarantee the
3.3V transmitter functions with a falling edge strobe pin
17 should be connected to ground OR left unconnected.
When not connected (left open) and internal pull-down
resistor ties pin 17 to ground, thus configuring the trans-
mitter with a falling edge strobe.
3.
The DS90C383 transmitter input and control inputs ac-
cept 3.3V TTL/CMOS levels. They are not 5V tolerant.
DS012887-21
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 10: Cycle-to-cycle jitter is less than 250 ps at 65 MHZ
Note 11: ISI is dependent on interconnect length; may be zero
FIGURE 19. Receiver LVDS Input Skew Margin
www.national.com
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