DS90C387A/DS90CF388A

Dual Pixel LVDS Display Interface / FPD-Link

General Description

The DS90C387A/DS90CF388A transmitter/receiver pair is

designed to support dual pixel data transmission between

Host and Flat Panel Display up to QXGA resolutions. The

transmitter converts 48 bits (Dual Pixel 24-bit color) of

CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage

Differential Signalling) data streams. At a maximum dual

pixel rate of 112MHz, LVDS data line speed is 784Mbps,

providing a total throughput of 5.7Gbps (714 Megabytes per

second).

The LDI chipset is improved over prior generations of FPD-

Link devices and offers higher bandwidth support and longer

cable drive. To increase bandwidth, the maximum pixel clock

rate is increased to 112 MHz and 8 serialized LVDS outputs

are provided. Cable drive is enhanced with a user selectable

pre-emphasis feature that provides additional output current

during transitions to counteract cable loading effects.

The DS90C387A transmitter provides a second LVDS output

clock. Both LVDS clocks are identical. This feature supports

backward compatibility with the previous generation of FPD-

Link Receivers - the second clock allows the transmitter to

interface to panels using a ’dual pixel’ configuration of two

24-bit or 18-bit FPD-Link receivers.

This chipset is an ideal means to solve EMI and cable size

problems for high-resolution flat panel applications. It pro-

vides a reliable interface based on LVDS technology that

delivers the bandwidth needed for high-resolution panels

while maximizing bit times, and keeping clock rates low to

reduce EMI and shielding requirements. For more details,

please refer to the “Applications Information” section of this

datasheet.

Features

n

Supports SVGA through QXGA panel resolutions

n

32.5 to 112/170MHz clock support

n

Drives long, low cost cables

n

Up to 5.7 Gbps bandwidth

n

Pre-emphasis reduces cable loading effects

n

Dual pixel architecture supports interface to GUI and

timing controller; optional single pixel transmitter inputs

support single pixel GUI interface

n

Transmitter rejects cycle-to-cycle jitter

n

5V tolerant on data and control input pins

n

Programmable transmitter data and control strobe select

(rising or falling edge strobe)

n

Backward compatible with FPD-Link

n

Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard

Generalized Transmitter Block Diagram

10132002

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

February 2006

© 2006 National Semiconductor Corporation

DS101320

www.national.com