LM8333

SNLS246K – SEPTEMBER 2006 – REVISED MAY 2013

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WATCHDOG TIMER

The watchdog timer is always enabled in hardware. To use the timer, connect the WD_OUT output to the

RESET input.

HALT MODE

The fully static architecture of the LM8333 allows stopping the internal RC clock in Halt mode, which reduces

power consumption to the minimum level.

Halt mode is entered when no key-press, key-release, or ACCESS.bus activity is detected for a certain period of

time (by default, 500 milliseconds). The mechanism for entering Halt mode is always enabled in hardware, but

the host can program the period of inactivity which triggers entry into Halt mode.

The LM8333 will remain in Active mode as long as a key event, or any other event, which causes the IRQ output

to be asserted is not resolved.

ACCESS.bus Activity

When the LM8333 is in Halt mode, any activity on the ACCESS.bus interface will cause the LM8333 to exit from

Halt mode. However, the LM8333 will not be able to acknowledge the first bus cycle immediately following wake-

up from Halt mode. It will respond with a negative acknowledgement, and the host should then repeat the cycle.

The LM8333 will be prevented from entering Halt mode if it shares the bus with peripherals that are continuously

active. For lowest power consumption, the LM8333 should only share the bus with peripherals that require little

or no bus activity after system initialization.

KEYPAD SCANNING

The LM8333 starts new scanning cycles at fixed time intervals of about 4 ms. If a change in the state of the

keypad is detected, the keypad is rescanned after a debounce delay. When the state change has been reliably

captured, it is encoded and written to the FIFO buffer.

If more than two keys are pressed simultaneously, the pattern of key closures may be ambiguous, so pressing

more than two keys asserts the Error Flag condition and the IRQ output (if enabled). The host may attempt to

interpret the events stored in the FIFO or discard them.

The SF keys connect the WAKE_INx pins directly to ground. There can be up to eight SF-keys. If any of these

keys are pressed, other key presses that use the same WAKE_INx pin will be ignored.

COMMUNICATION INTERFACE

The two-wire ACCESS.bus interface is used to communicate with a host. The ACCESS.bus interface is fully

compliant with the I2Cbus standard. The LM8333 operates as a bus slave at speeds up to 400 kHz.

An ACCESS.bus transfer starts with a byte that includes a 7-bit slave device address. The LM8333 responds to

a fixed device address. This address is 0xA2, when aligned to the MSB (7-bit address mapped to bits 7:1, rather

than bits 6:0). Bit 0 is a direction bit (0 on write, 1 on read).

Because it is a slave, the LM8333 never initiates an ACCESS.bus cycle, it only responds to bus cycles initiated

by the host. The LM8333 may signal events to the host by asserting the IRQ interrupt request.

Interrupts Between the Host and LM8333

The IRQ output is used to signal unresolved interrupts, errors, and key-events to the host.

The host can use an available GEN_IO_0 or GEN_IO_1 pin to interrupt (or wake-up) the LM8333, if it is not

being used for another function. The host can also wake-up the LM8333 by sending a Start Condition on the

ACCESS.bus interface.

NOTE

The LM8333 it will not be able to acknowledge the first byte received from the host after

wake-up. In this case, the host will have to resend the slave address.

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