LMC7660

SNOSBZ9C – APRIL 1997 – REVISED APRIL 2013

www.ti.com

LOWERING OUTPUT IMPEDANCE

Paralleling two or more LMC7660's lowers output impedance. Each device must have it's own pumping capacitor

Cp, but the reservoir capacitor Cr is shared as depicted in Figure 14. The composite output resistance is:

(3)

INCREASING OUTPUT VOLTAGE

Stacking the LMC7660s is an easy way to produce a greater negative voltage. It should be noted that the input

current required for each stage is twice the load current on that stage as shown in Figure 15. The effective output

resistance is approximately the sum of the individual Rout values, and so only a few levels of multiplication can be

used.

It is possible to generate

−15V from +5V by connecting the second 7660's pin 8 to +5V instead of ground as

shown in Figure 16. Note that the second 7660 sees a full 20V and the input supply should not be increased

beyond +5V.

Figure 14. Lowering Output Resistance by Paralleling Devices

Figure 15. Higher Voltage by Cascade

Figure 16. Getting

−15V from +5V

8

Submit Documentation Feedback

Copyright © 1997–2013, Texas Instruments Incorporated

Product Folder Links: LMC7660