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LMH6574

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SNCS103E – NOVEMBER 2004 – REVISED AUGUST 2018

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Copyright © 2004–2018, Texas Instruments Incorporated

(1)

Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device such that TJ = TA. No ensure of parametric performance is indicated in the electrical tables under

conditions of internal self heating where TJ > TA. See Application and Implementation for information on temperature de-rating of this

device. Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted.

(2)

Parameters guaranteed by electrical testing at 25°C.

(3)

Positive Value is current into device.

6.5 Electrical Characteristics ±5 V

VS = ±5 V, RL = 100 Ω, AV = 2 V/V, RF = 575 Ω, TJ = 25 °C, unless otherwise specified.

PARAMETER

TEST CONDITIONS(1)

MIN

TYP

MAX

UNIT

FREQUENCY DOMAIN PERFORMANCE

SSBW

−3 dB Bandwidth

VOUT = 0.5 VPP

500

MHz

LSBW

–3 dB Bandwidth

VOUT = 2 VPP

400

MHz

.1 dBBW

0. 1 dB Bandwidth

VOUT = 0.25 VPP

150

MHz

DG

Differential Gain

RL = 150 Ω, f = 4.43 MHz

0.02%

DP

Differential Phase

RL = 150 Ω, f = 4.43 MHz

0.05

deg

XTLK

Channel to Channel

Crosstalk

All Hostile, 5 MHz

−85

dB

TIME DOMAIN RESPONSE

TRS

Channel to Channel

Switching Time

Logic Transition to 90% Output

8

ns

Enable and Disable

Times

Logic Transition to 90% or 10% Output

10

ns

TRL

Rise and Fall Time

4-V Step

2.4

ns

TSS

Settling Time to 0.05%

2-V Step

17

ns

OS

Overshoot

2-V Step

5%

SR

Slew Rate

4-V Step

2200

V/μs

DISTORTION

HD2

2nd Harmonic Distortion

2 VPP , 5 MHz

−68

dBc

HD3

3rd Harmonic Distortion

2 VPP , 5 MHz

−84

dBc

IMD

3rd Order

Intermodulation

Products

10 MHz, Two Tones 2 VPP at Output

−80

dBc

EQUIVALENT INPUT NOISE

VN

Voltage

>1 MHz, Input Referred

5

nV

√Hz

ICN

Current

>1 MHz, Input Referred

5

pA/

√Hz

STATIC, DC PERFORMANCE

CHGM

Channel to Channel

Gain Difference

DC, Difference in Gain

Between Channels

±0.005%

±0.032%

-40°C

≤ TJ ≤ 85°C

±0.035%

VIO

Input Offset Voltage(2)

VIN = 0 V

1

±20

mV

-40°C

≤ TJ ≤ 85°C

±25

DVIO

Offset Voltage Drift

30

µV/°C

IBN

Input Bias Current(2)(3)

VIN = 0 V

−3

±5.2

µA

-40°C

≤ TJ ≤ 85°C

±5.8

DIBN

Bias Current Drift

11

nA/°C

Inverting Input Bias

Current

Pin 12, Feedback Point,

VIN = 0 V

−7

±10

-40°C

≤ TJ ≤ 85°C

±13

PSRR

Power Supply Rejection

Ratio(2)

DC, Input Referred

43

54

dB

-40°C

≤ TJ ≤ 85°C

41